Tensile-Strained FinFET Isolation via Ge Oxidation

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Solution Overview

Problem

The integration of alternative semiconductor materials like SiGe and III-V on silicon substrates is challenging due to lattice mismatch issues, and traditional manufacturing techniques struggle to form fins with precise strain conditions for both NMOS and PMOS devices, affecting device performance.

Innovation Solution

A method involving the formation of a composite fin structure with a germanium-containing semiconductor material and a tensile-strained semiconductor material, followed by a thermal anneal process to convert the germanium-containing material into a germanium-containing oxide isolation region, creating tensile-strained fins for NMOS FinFET devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If alternative semiconductor materials like SiGe and III-V are integrated on silicon substrates, then device performance and charge carrier mobility are enhanced, but lattice mismatch issues arise causing manufacturing challenges

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing challenges
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A silicon-germanium buffer layer is introduced as an intermediary between the silicon substrate and the alternative semiconductor material (such as III-V materials). This buffer layer has a graded germanium concentration that gradually transitions from the silicon substrate to the alternative material, serving as a mediator that reduces the lattice mismatch and dislocation density, thereby enabling successful integration while maintaining device performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The germanium concentration in the buffer layer is gradually changed from the silicon substrate (0% Ge) to the alternative material composition through a graded structure. This parameter change in composition allows the lattice constant to transition smoothly, reducing the harmful effects of lattice mismatch and enabling the integration of high-performance alternative materials on silicon substrates

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If traditional manufacturing techniques are used to form fins, then process simplicity is maintained, but precise strain conditions for both NMOS and PMOS devices cannot be achieved

Engineering Contradiction:
Improveprocess simplicityVSAvoidstrain conditions precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

Different fin structures with different strain conditions are created in different regions of the semiconductor device. NMOS fins are formed with tensile strain through specific crystallographic orientations and material compositions, while PMOS fins are formed with compressive strain. This local differentiation of strain conditions allows precise control over device characteristics for each transistor type while maintaining a relatively simple overall manufacturing process

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The fin formation process is segmented into distinct pathways for NMOS and PMOS devices. By dividing the manufacturing process into separate sequences that apply different strain conditions to different fin regions, the method achieves precise strain control for each device type. This segmentation allows independent optimization of NMOS and PMOS performance without compromising process simplicity

Inventive Principle:
Principle #1Segmentation

3Reliability

If fins are formed with precise strain conditions, then device performance is improved, but fin isolation region formation becomes challenging

Engineering Contradiction:
Improvedevice performanceVSAvoidisolation region formation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The silicon-germanium buffer layer serves as an intermediary structure that facilitates both the strain condition formation and the subsequent isolation region creation. The graded composition of the buffer layer enables precise strain control in the overlying semiconductor material while also providing a controlled interface for forming the fin isolation region, thereby reducing the overall device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The fin isolation region formation process is merged with the strain condition establishment. The silicon-germanium buffer layer that creates the strain in the fin is simultaneously used as the material from which the isolation region is formed through selective oxidation. This merging of functions reduces the number of separate process steps needed, thereby reducing device complexity while maintaining precise strain conditions for improved performance

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the precise formation of tensile-strained fin isolation regions, enhancing NMOS device performance while allowing for the potential integration of alternative materials, improving device performance without degrading operating speed.

Implementation Method 1

performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of composite fin structure into a germanium-containing oxide isolation region

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

performing a thermal anneal process to convert the first germanium-containing semiconductor material portion

Methodology Applied
Scientific EffectThermal anneal: Annealing

Data Source

PatentUS10026659B2Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices
Publication Date: 2018.07.17 GLOBALFOUNDRIES US INC
  • US10026659B2 patent drawing
  • US10026659B2 patent drawing
  • US10026659B2 patent drawing

AI summary

One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.