FinFET Isolation Layer Height Control via Pseudo Gate Removal
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Solution Overview
Problem
In FinFET semiconductor device manufacturing, the removal of a pseudo gate can inadvertently or sacrificially remove a portion of the isolation layer, leading to a larger height of the semiconductor fin below the gate compared to the source and drain regions, reducing the active region volume and compromising both DC and AC performance.
Innovation Solution
A method involving the removal of a predetermined depth of the second region of the isolation layer, followed by epitaxial growth of source and drain regions, and forming a gate structure in a groove, to ensure the upper surfaces of the first and second regions are approximately leveled, thereby increasing the active region volume and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the pseudo gate is removed to form a gate structure, then the gate structure can be formed properly, but a portion of the isolation layer is inadvertently removed, causing the semiconductor fin height to be larger than the source and drain regions
Solution Approach 1:
The patent applies preliminary action by removing a predetermined depth of the second region of the isolation layer before forming the gate structure. This pre-removal step ensures that when the pseudo gate is subsequently removed, the isolation layer height remains consistent across different regions, preventing the semiconductor fin from being excessively tall relative to the source and drain regions.
2Ease of manufacture
If the isolation layer is removed during pseudo gate removal, then the gate structure can be formed, but the active region volume is reduced, compromising DC and AC performance
Solution Approach 1:
The patent performs preliminary removal of the second region of the isolation layer to a predetermined depth before gate formation. This ensures that the isolation layer maintains appropriate height relationships, thereby preserving active region volume and ensuring both DC and AC performance requirements are met while still allowing proper gate structure formation.
Solution Approach 2:
The patent changes the depth parameter of the isolation layer removal by specifying a predetermined removal depth for the second region. This parameter control ensures that the isolation layer height is optimized to maintain both manufacturability and device performance, preventing excessive fin height that would reduce active region volume.
3Ease of manufacture
If the semiconductor fin height is larger than source and drain regions, then the gate structure can accommodate the fin, but the active region volume is small, reducing AC performance
Solution Approach 1:
The patent applies preliminary action by removing a predetermined depth of the second region of the isolation layer before forming the gate structure. This pre-removal step ensures that when the pseudo gate is subsequently removed, the isolation layer height remains consistent across different regions, preventing the semiconductor fin from being excessively tall relative to the source and drain regions.
4Ease of manufacture
If the isolating layer around source/drain is above the isolating layer below gate, then source/drain isolation is improved, but DC performance is affected and impedance increases
Solution Approach 1:
The patent changes the depth parameter of the isolation layer removal by specifying a predetermined removal depth for the second region. This parameter control ensures that the isolation layer height is optimized to maintain both manufacturability and device performance, preventing excessive fin height that would reduce active region volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the DC and AC performance of the FinFET device by maintaining the height of the semiconductor fin above the isolating layer consistent with the source and drain regions, increasing the active region volume and responsiveness.
Implementation Method 1
growing an epitaxial source and drain on the semiconductor fin on sides of the pseudo gate
Data Source
AI summary
This disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing semiconductor FinFET devices. The method particularly includes pre-removal of a predetermined thickness of a first region of an isolation region on sides of a fin that is not covered by a pseudo gate such that when a layer of second region of the isolation region covered by the pseudo gate is sacrificially removed during a removal of the pseudo gate, the upper surfaces of the remaining first region and the remaining second region of the isolation region are approximately leveled. By using such a method, DC and AC performances of a resulting FinFET device is improved.