FinFET Isolation Liners for Uniform Fin Width and Lower Leakage

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Solution Overview

Problem

The scaling down of FinFET technologies leads to differences in critical dimensions of silicon and silicon germanium fins after fabrication stages, particularly during annealing processes, due to varying etching and oxidation rates, resulting in fin width discrepancies that affect device performance and lead to short-channel effects and increased leakage paths.

Innovation Solution

Implementing different isolation liners for n-type and p-type FinFETs, such as an oxide liner for n-type FinFETs and a combination of oxide and nitride liners for p-type FinFETs, to balance fin width consumption during isolation feature formation, and removing the nitride liner from n-type FinFETs to reduce leakage paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different fin materials (silicon and silicon germanium) are used for n-type and p-type FinFETs, then device performance is enhanced through material optimization, but fin width uniformity deteriorates due to different etching and oxidation rates during annealing processes

Engineering Contradiction:
Improvedevice performanceVSAvoidfin width uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by implementing different isolation liner configurations for n-type and p-type FinFETs. Specifically, n-type FinFETs receive isolation liners with a first thickness while p-type FinFETs receive isolation liners with a second thickness (different from the first). This localized differentiation compensates for the inherent material property differences between silicon and silicon germanium fins, ensuring uniform fin width consumption during annealing processes while preserving the performance benefits of material-specific optimization.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If standard isolation liners are used for all FinFET types, then manufacturing process is simplified, but fin width consumption varies causing critical dimension control issues

Engineering Contradiction:
Improveisolation feature fabricationVSAvoidcritical dimension control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent implements local quality by configuring isolation liners with different thicknesses for n-type and p-type FinFETs. This approach maintains manufacturing precision by compensating for material-specific etching and oxidation rate differences, while the process remains relatively simple through selective application of different liner thicknesses based on FinFET type.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If annealing processes are performed during isolation feature formation, then isolation features are successfully formed, but fin width consumption occurs differently for silicon and silicon germanium fins

Engineering Contradiction:
Improveisolation feature formationVSAvoidfin width consistency
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the isolation liner thickness parameter based on FinFET type. During annealing processes, n-type FinFETs are exposed to isolation liners with a first thickness while p-type FinFETs have isolation liners with a second thickness. This parameter differentiation compensates for the different etching and oxidation rates of silicon and silicon germanium materials, ensuring uniform fin width consumption while maintaining successful isolation feature formation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach achieves uniform fin widths and reduces leakage currents, improving the performance and reliability of FinFET devices by minimizing fin width differences and eliminating fixed charge-induced leakage paths.

Implementation Method 1

different fin materials respond differently to subsequent processing... during annealing processes associated with forming isolation features

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

Implementing different isolation liners for n-type and p-type FinFETs, such as an oxide liner for n-type FinFETs and a combination of oxide and nitride liners for p-type FinFETs

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11848230B2Different isolation liners for different type FinFETs and associated isolation feature fabrication
Publication Date: 2023.12.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11848230B2 patent drawing
  • US11848230B2 patent drawing
  • US11848230B2 patent drawing

AI summary

Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).