FinFET Isolation Liners for Uniform Fin Width Across Si and SiGe
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Solution Overview
Problem
Different fin materials in FinFETs respond differently to processing, leading to inconsistent fin width consumption during isolation feature formation, which affects the performance and integrity of silicon and silicon germanium fins, particularly in n-type and p-type FinFETs.
Innovation Solution
Implementing different isolation liners for n-type and p-type FinFETs, with oxide liners for both types and an additional nitride liner for p-type FinFETs, to balance fin width consumption and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different fin materials (silicon and silicon germanium) are used for n-type and p-type FinFETs, then device performance is enhanced through material optimization, but fin width consumption becomes inconsistent during isolation feature formation
Solution Approach 1:
The patent applies different isolation liner configurations to different FinFET types: n-type FinFETs receive oxide liners only, while p-type FinFETs receive both oxide and nitride liners. This local differentiation compensates for the different consumption rates of silicon versus silicon germanium fins during isolation annealing, ensuring uniform fin widths across device types while preserving the performance benefits of material selection
Solution Approach 2:
The patent modifies the isolation liner composition parameter (adding nitride liner specifically to p-type FinFETs) to counteract the differential fin width consumption. The nitride liner provides additional protection during annealing processes, adjusting the effective protection parameter to achieve consistent fin widths despite different base materials
2Device complexity
If a single isolation liner configuration is used for both n-type and p-type FinFETs, then process complexity is reduced, but fin width uniformity deteriorates due to different material responses
Solution Approach 1:
Rather than using a uniform isolation liner configuration across all devices, the patent implements location-specific liner assignments: oxide liners for n-type regions and combined oxide-nitride liners for p-type regions. This approach accepts increased process complexity as necessary to achieve the critical fin width uniformity required for consistent device performance
3Ease of manufacture
If oxide liner only is used for both FinFET types, then manufacturing process is simplified, but current leakage paths increase in p-type FinFETs
Solution Approach 1:
The patent identifies that p-type FinFETs specifically benefit from the additional nitride liner layer, which provides superior protection against current leakage paths during isolation formation. While this increases complexity compared to a universal oxide-liner approach, the targeted application of nitride liners only where needed (p-type regions) minimizes the overall process complexity increase while effectively eliminating the leakage issue
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The combination of isolation liners ensures uniform fin widths and reduces current leakage paths, enhancing the performance and reliability of FinFET devices by minimizing detrimental short-channel effects and optimizing gate formation.
Implementation Method 1
an oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the second region
Implementation Method 2
an oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the second region
Implementation Method 3
An isolation material is formed over the oxide liner and the nitride liner. The isolation material fills the first trenches and the second trenches
Data Source
AI summary
Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).