FinFET Isolation Oxide Thickness Control via HDPCVD
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Solution Overview
Problem
Conventional methods for forming shallow trench isolation in FinFET devices face challenges in controlling the thickness of dielectric layers, reliably filling high aspect ratio trenches, and minimizing fin height variability, especially in bulk silicon wafers without an etch stop layer, leading to electrical isolation issues and variability in current conductivity.
Innovation Solution
The method involves using high density plasma chemical vapor deposition (HDPCVD) to deposit an oxide layer with a greater thickness at the bottom of isolation trenches than on vertical sidewalls, followed by isotropic etching to create a uniformly thick isolating oxide layer, reducing the need for excess dielectric material and minimizing fin height variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional STI process with excess dielectric deposition and CMP planarization is used, then electrical isolation between fins is achieved, but the dielectric layer thickness varies and fin height variability increases
Solution Approach 1:
The patent applies preliminary action by depositing the exact amount of dielectric material needed to fill the isolation trench to the desired final thickness, eliminating the need for subsequent CMP planarization and etch back steps. This preliminary precise deposition ensures uniform dielectric layer thickness without variability, directly resolving the contradiction between achieving electrical isolation and maintaining manufacturing precision.
2Reliability
If conventional STI process with etch back is used, then isolation trenches are filled, but more dielectric filler material than needed is deposited
Solution Approach 1:
The patent applies partial action by depositing dielectric material to exactly the required thickness for isolation, avoiding the conventional approach of excessive deposition followed by removal. This precise partial deposition eliminates waste of dielectric filler material while still achieving complete and reliable isolation trench filling.
3Adaptability or versatility
If bulk silicon wafer is used without etch stop layer, then FinFET device fabrication is enabled, but fin height variability increases due to etch depth variability
Solution Approach 1:
The patent applies parameter changes by modifying the dielectric deposition process parameters to achieve precise thickness control. By using controlled dielectric deposition with monitored thickness parameters, the process compensates for the lack of etch stop layer, ensuring uniform fin height despite variations in etch depth on bulk silicon wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables controlled and uniform filling of high aspect ratio trenches, reducing fin height variability and improving electrical isolation between fin structures, resulting in more consistent current conductivity and fewer processing steps.
Implementation Method 1
An oxide layer is deposited in the bottom of the isolation trenches and on the vertical sidewalls of the one or more fin structures using a high density plasma chemical vapor deposition (HDPCVD) process.
Implementation Method 2
high density plasma chemical vapor deposition (HDPCVD)
Implementation Method 3
The oxide layer is then removed from the vertical sidewalls and at least a portion is removed from the isolation trenches to form a substantially uniformly thick isolating oxide layer in the isolation trenches.
Data Source
AI summary
Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.