FinFET Source/Drain Isolation Plug for Lower RC Layout
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher device density, performance, and lower costs, particularly in the fabrication and design of FinFETs and other MOSFETs, where current methods struggle to optimize current flow and reduce short-channel effects effectively.
Innovation Solution
The method involves forming semiconductor fins with an isolation dielectric plug between them, allowing for the growth of enlarged epitaxial source/drain structures without contact, and creating air gaps to reduce parasitic capacitance, thereby enhancing electrical resistance and capacitance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain structures are enlarged to increase contact area, then electrical resistance is improved, but device area increases
Solution Approach 1:
The source/drain structures transition from planar 2D configurations to 3D FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective contact area and current flow path without proportionally increasing the planar device footprint, thereby improving electrical resistance while maintaining compact device area.
2Reliability
If air gaps are introduced to reduce parasitic capacitance, then RC performance is improved, but manufacturing complexity increases
Solution Approach 1:
The isolation dielectric layer is segmented to create discrete air gaps between adjacent FinFET devices. Instead of a continuous dielectric layer, the isolation is divided into sections with intentional voids, reducing parasitic capacitance between neighboring devices while maintaining electrical isolation. This segmented approach improves RC performance with manageable manufacturing complexity.
3Productivity
If FinFET dimensions are reduced to increase device density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The FinFET structure utilizes vertical scaling by changing the dimensional parameters from lateral planar dimensions to vertical height dimensions. The channel length is defined by the fin height rather than lateral spacing, allowing increased device density without proportionally reducing all dimensional parameters. This parameter transformation relaxes manufacturing precision requirements while maintaining high device density.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, first and second semiconductor fins extending from the semiconductor substrate, a gate structure, first source/drain epitaxial structures, second source/drain epitaxial structures, and an isolation dielectric plug. The gate structure extends cross the first and second semiconductor fins. The first and second source/drain epitaxial structures are over the first and second semiconductor fins, respectively. The isolation dielectric plug extends between a first one of the first source/drain epitaxial structures and a first one of the second source/drain epitaxial structures along a first direction parallel to longitudinal axes of the first and second semiconductor fins. The isolation dielectric plug has a U-shape profile when viewed in a cross section taken along a second direction parallel to a longitudinal axis of the gate structure.