FinFET Fin Isolation Positioning for Uniform Etching
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Solution Overview
Problem
The downsizing of FinFETs makes it difficult to uniformly form a large number of FinFETs, leading to variations in fin shape and etching conditions, which affects the uniformity and characteristics of the transistors.
Innovation Solution
The formation of both standard and wide fins on a semiconductor substrate, with a device isolation insulating film positioned differently between them, allows for uniform etching and reduced microloading effects, enabling consistent FinFET formation across the integrated circuit device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If FinFETs are downsized to increase integration density, then the device area is reduced, but the uniformity of fin shape and etching conditions deteriorates
Solution Approach 1:
The patent applies local quality by creating two types of fins with different widths (first fins and second fins) at different locations on the semiconductor substrate. The device isolation insulating film is positioned at different heights relative to the upper ends of these fins, creating locally optimized etching conditions for each fin type. This allows uniform etching across differently sized fins while maintaining high integration density.
2Ease of manufacture
If standard etching processes are used for uniformly forming multiple FinFETs, then the process is simple, but variations in fin shape occur due to microloading effects
Solution Approach 1:
The patent changes the physical parameters of the etching process by introducing device isolation insulating film at different positions for different fin types. This creates different local etching environments that compensate for microloading effects, allowing uniform fin formation across the substrate while maintaining a relatively simple single-etching-process approach.
3Manufacturing precision
If planarization treatments are applied to ensure uniform FinFET characteristics, then the manufacturing precision is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent performs preliminary action by pre-positioning the device isolation insulating film at different heights relative to different fin types before the etching process. This preliminary structuring creates self-aligning etching conditions that automatically compensate for variations, eliminating the need for subsequent planarization treatments and reducing manufacturing complexity.
Data Source
AI summary
An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.