FinFET Isolation Structure for Punch-Through Prevention
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Solution Overview
Problem
The short-channel effects in semiconductor devices, such as MOSFETs, lead to subthreshold leakage and reduced control of the gate over the channel, especially as feature sizes decrease, necessitating improved electrical properties and isolation between source/drain regions and wells in semiconductor structures.
Innovation Solution
A method involving the formation of a protective sidewall on fins in semiconductor structures, where the sidewall exposes a lower portion and covers an upper portion, allowing for partial etching and subsequent oxidation to create an isolation structure that separates the source/drain regions from the wells, enhancing the isolation effect and preventing punch-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length of MOSFETs is shortened to adapt to reduced feature size, then the device can accommodate smaller dimensions, but the controlling capability of gate to channel is degraded and short-channel effects occur more easily
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, utilizing three-dimensional vertical fins to enhance gate control. The gate wraps around the fin from multiple sides, providing superior electrostatic control over the channel despite shortened channel lengths, thereby resolving the degradation of gate control capability while maintaining small feature sizes
2Length of moving object
If the channel length is shortened, then the device size is reduced, but the distance between source and drain is shortened causing subthreshold leakage phenomenon
Solution Approach 1:
The FinFET structure provides enhanced gate control from multiple sides, effectively suppressing subthreshold leakage that occurs in planar devices with short channels
Solution Approach 2:
The patent forms an isolation structure between the source/drain regions and the N-type/P-type wells before final device fabrication. This preliminary isolation prevents punch-through effects and reduces subthreshold leakage by electrically separating the source/drain regions from the doped wells, addressing the leakage issue before it manifests in the completed device
3Length of moving object
If current fabrication technologies are used, then devices can be manufactured with reduced feature size, but the electrical properties of the semiconductor devices need to be improved
Solution Approach 1:
The FinFET structure provides superior electrical properties through three-dimensional gate control, achieving better electrostatic performance and lower leakage compared to planar devices at the same feature size
Solution Approach 2:
The preliminary formation of isolation structures between source/drain regions and doped wells enhances electrical properties by preventing unwanted charge carrier injection and reducing punch-through effects, thereby improving device reliability before final characterization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical performance by enhancing the isolation between source/drain regions and wells, reducing punch-through and thereby improving the overall performance of semiconductor devices like SRAM transistors.
Implementation Method 1
forming an isolation structure at least by oxidizing the remaining lower portion of the fin
Data Source
AI summary
A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a plurality of fins on a substrate including an NMOS region and a PMOS region adjacent to the NMOS region; forming an N-type well in the PMOS region and a P-type well in the NMOS region of the substrate; forming a protective sidewall to cover an upper portion of a sidewall surface of each fin in each of the NMOS region and PMOS region and to expose a lower portion of the sidewall surface of each fin; removing a partial width of the lower portion of the fin using the protective sidewall as an etch mask; removing the protective sidewall; and forming an isolation structure at least by oxidizing the remaining lower portion of the fin and having a top surface lower than the neighboring upper portions of the fins.