FinFET Device Isolation via Sacrificial Gate Etching
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Solution Overview
Problem
There is a need for improved manufacturing methods for semiconductor devices that enhance isolation between transistors, particularly for multi-gate transistors with fin-shaped active patterns, to address the challenges of scaling and short channel effects as semiconductor devices become smaller.
Innovation Solution
The method involves forming sacrificial gate insulating layers and electrodes on fins, followed by etching processes to create trenches and recesses, and filling these with device isolation layers, which helps in improving isolation characteristics and reducing the height of fins to minimize electrical conductivity differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors with fin-shaped active patterns are used to increase integration density, then scaling capability and current control improve, but isolation between transistors becomes more difficult to achieve
Solution Approach 1:
The substrate is divided into multiple isolated fin regions separated by device isolation layers. Each fin structure is independently isolated from adjacent fins through the formation of trenches filled with insulating material, enabling high integration density while maintaining electrical isolation between transistor channels
Solution Approach 2:
Device isolation layers serve as intermediary insulating structures positioned between adjacent fin-shaped active patterns. These isolation layers act as electrical barriers that prevent unwanted current flow between neighboring transistors while allowing each fin to function independently as a multi-gate transistor channel
2Reliability
If device isolation is enhanced through multiple etching processes, then isolation characteristics improve, but fin height is reduced creating electrical conductivity differences
Solution Approach 1:
Sacrificial gate insulating layers and sacrificial gate electrodes are formed on the fins before the device isolation etching processes. These preliminary structures serve as protective masks during the first and second etching processes, preventing excessive removal of fin material and maintaining fin height uniformity while still allowing effective isolation to be achieved
Solution Approach 2:
Different etching selectivities are utilized between the first etching process (for device isolation trenches) and the third etching process (for source/drain regions). By controlling etching parameters such as gas composition, power, and pressure, the process selectively removes sacrificial materials and forms isolation trenches without significantly altering fin height, thereby maintaining electrical conductivity uniformity
3Reliability
If multiple etching processes are used to form trenches and recesses, then device isolation quality improves, but manufacturing complexity increases
Solution Approach 1:
Sacrificial gate insulating layers and sacrificial gate electrodes are formed in advance before the device isolation etching processes. These preliminary structures serve as self-aligned masks that define the trench patterns, eliminating the need for separate photolithography alignment steps and simplifying the overall manufacturing process despite multiple etching steps
Solution Approach 2:
The sacrificial gate electrodes serve multiple functions: they act as masks during the first etching process to define device isolation trenches, serve as structural templates for subsequent source/drain formation, and can be selectively removed later. This multi-functionality reduces the total number of separate manufacturing steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances device isolation, reduces the height of fin fences, and improves carrier mobility, thereby addressing the scaling and short channel effect challenges in semiconductor devices.
Implementation Method 1
removing the exposed second sacrificial gate electrode using a first etching process to expose the second sacrificial gate insulating layer
Implementation Method 2
removing the exposed second sacrificial gate insulating layer using a second etching process different from the first etching process to form a first trench
Implementation Method 3
forming a first recess in the exposed first fin through a third etching process, different from the second etching process
Data Source
AI summary
Methods are provided for manufacturing semiconductor devices include forming a first fin protruding on a substrate and extending in a first direction; forming first and second sacrificial gate insulating layers on the first fin, the first and second sacrificial gate insulating layers intersecting the first fin and being spaced apart from each other; forming first and second sacrificial gate electrodes respectively on the first and second sacrificial gate insulating layers; forming a first insulating layer on the first and second sacrificial gate electrodes; removing a portion of the first insulating layer to expose the second sacrificial gate electrode; removing the exposed second sacrificial gate electrode using a first etching process to expose the second sacrificial gate insulating layer; removing the exposed second sacrificial gate insulating layer using a second etching process different from the first etching process to form a first trench which exposes the first fin; forming a first recess in the exposed first fin using a third etching process different from the second etching process; and filling the first recess with a first device isolation layer.