FinFET Isolation Gate Layout for SiGe Strain Retention
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Solution Overview
Problem
FinFET fabrication methods face challenges in optimizing isolation structures to prevent strain loss in SiGe fins and maintain scaling capability, particularly in forming dielectric dummy gates and isolation gates without additional gate cut processes.
Innovation Solution
The approach involves forming FinFET cells with reduced strain loss in SiGe fins without the additional gate cut process, using dielectric plugs and fins to provide electrical isolation between circuit cells, and employing a method that includes forming semiconductor fins, dielectric fins, and gate structures without breaking up continuous isolation gates across P-type and N-type wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional gate cut processes are used to form dielectric dummy gates and isolation gates, then electrical isolation between circuit cells is achieved, but device complexity and fabrication process steps increase
Solution Approach 1:
The isolation gate structure is segmented into multiple portions (first portion over P-type well, second portion over N-type well) that are formed simultaneously in a single continuous process without requiring intermediate gate cuts, achieving electrical isolation while simplifying fabrication
Solution Approach 2:
The formation of dielectric dummy gates and isolation gates is merged into a single simultaneous process step, where both structures are formed together without requiring additional gate cut processes, reducing device complexity while maintaining electrical isolation
2Productivity
If FinFET geometry is scaled down to increase functional density, then production efficiency improves, but maintaining strain in SiGe fins becomes more difficult
Solution Approach 1:
Different regions of the isolation gate structure are designed with different properties (first portion over P-type well, second portion over N-type well) to locally optimize strain maintenance in SiGe fins while enabling continued scaling for improved productivity
Solution Approach 2:
The continuous isolation gate structure is formed preliminarily during the same process step as dielectric dummy gates, establishing strain-maintaining structures before subsequent fabrication steps, enabling scaling without compromising strain in SiGe fins
3Area of stationary object
If dielectric plugs are used to provide electrical isolation, then chip area efficiency improves, but additional process steps are required
Solution Approach 1:
The formation of dielectric plugs and isolation structures is merged into a single integrated process, where dielectric material is deposited to form both plugs and isolation gates simultaneously, achieving chip area efficiency without adding separate process steps
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.