FinFET Isolation Gate Design for Strain Preservation in SiGe Fins
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Solution Overview
Problem
FinFET fabrication methods face challenges in optimizing isolation structures between neighboring circuit cells, leading to strain loss in SiGe fins and complicating the scaling down process due to the need for additional gate cut processes.
Innovation Solution
The implementation of FinFET cells with reduced strain loss in SiGe fins, fabricated without the additional gate cut process to separate isolation gates between N-type and P-type wells, using continuous PMOSFET fins and discontinuous NMOSFET fins to prevent strain loss and facilitate scaling, along with dielectric dummy gates for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional gate cut processes are used to separate isolation gates between N-type and P-type wells, then isolation between circuit cells is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the isolation gate structure by making it continuous across both N-type and P-type wells without requiring separate gate cut processes. The isolation gate extends continuously over the fin structures in both well types, eliminating the need for additional processing steps to separate gates between different well regions.
Solution Approach 2:
The continuous isolation gate serves multiple functions simultaneously: it provides electrical isolation for both N-type and P-type circuit cells, maintains a regular gate arrangement across the entire device, and eliminates the need for separate processing steps for different well types.
2Ease of manufacture
If continuous fin structures are used across N-type and P-type wells, then manufacturing process is simplified, but strain loss in SiGe fins may occur
Solution Approach 1:
The patent applies different fin material compositions to different regions: SiGe fins are used in N-type wells where strain is beneficial for electron mobility, while Si fins are used in P-type wells. This local differentiation maintains strain in SiGe fins while allowing continuous fin structures across the entire device without requiring complex processing.
3Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved, but strain maintenance in SiGe fins becomes more difficult
Solution Approach 1:
By using SiGe fins only in N-type wells and Si fins in P-type wells, the patent maintains strain in the SiGe regions even as overall device dimensions scale down. The continuous fin structure allows this material differentiation to be implemented without increasing process complexity, enabling strain maintenance during scaling.
Data Source
AI summary
A semiconductor device includes a germanium-containing fin, a germanium-free fin, and an isolation gate. The germanium-containing fin extends a first length along a first direction within an N-type well region. The germanium-free fin extends a second length along the first direction within a P-type well region bordering the N-type well region. The second length of the germanium-free fin is less than the first length of the germanium-containing fin. The isolation gate extends across the germanium-containing fin along a second direction substantially perpendicular to the first direction, and terminates prior to reaching the germanium-free fin.