FinFET Isolation via Substrate Etching and Dielectric Fill

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Solution Overview

Problem

Conventional methods for manufacturing multigate devices, such as FinFETs, face challenges in achieving satisfactory device performance due to leakage current between fins, high processing complexity, and high manufacturing costs, particularly when scaling down Critical Dimension.

Innovation Solution

A method involving etching the semiconductor substrate to form a gap between the fin and the substrate, followed by forming and etching a dielectric layer to isolate fins, which reduces processing complexity and cost while ensuring effective isolation between fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation is used to form doped junction for isolation at the bottom of fins, then leakage current between adjacent fins is reduced, but the isolation quality is poor and the implantation process is hard to control

Engineering Contradiction:
Improveisolation qualityVSAvoidprocess control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a dielectric layer as an intermediary substance to achieve fin isolation. Instead of directly using ion implantation on the semiconductor substrate, the dielectric layer is deposited to fill the gap between fins and provide the isolation function, making the process more controllable and effective

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the approach from modifying the semiconductor substrate through ion implantation to depositing a dielectric material. This parameter change in the isolation method allows for better process control through standard deposition techniques rather than complex ion implantation parameters

Inventive Principle:
Principle #35Parameter changes

2Reliability

If selective lateral oxidation is performed to extend the dielectric layer laterally to isolate adjacent fins, then fin isolation is achieved, but the processing complexity increases and additional stress is introduced in the fin

Engineering Contradiction:
Improvefin isolationVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary etching to create gaps between fins before dielectric layer deposition. This preliminary action eliminates the need for subsequent lateral oxidation steps, reducing processing complexity while achieving the same isolation effect

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the complex lateral oxidation step from the process flow by pre-forming gaps through etching. This removes the source of processing complexity and stress introduction while maintaining the isolation function

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If SOI substrate is used to completely isolate adjacent fins, then fin isolation is achieved, but the manufacturing cost increases

Engineering Contradiction:
Improvefin isolationVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the substrate by etching gaps between fins and filling them with dielectric material. This creates isolated fin regions without requiring expensive SOI substrates, achieving the same isolation effect through a cost-effective bulk substrate approach

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a standard bulk semiconductor substrate instead of expensive SOI substrate. The temporary gaps created during processing are filled with inexpensive dielectric material, replacing the need for costly pre-isolated substrates

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for complete isolation of fins with reduced processing complexity and cost, making it suitable for massive industrial application and improving device performance.

Implementation Method 1

etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS8466028B2Method for manufacturing multigate device
Publication Date: 2013.06.18 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US8466028B2 patent drawing
  • US8466028B2 patent drawing
  • US8466028B2 patent drawing

AI summary

A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.