FinFET Isolation Layer Thinning for Stress Balance
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Solution Overview
Problem
In semiconductor manufacturing, the reduction in feature size of integrated circuits leads to Short-Channel Effects (SCE) due to reduced channel length in MOSFETs, causing subthreshold leakage and requiring more efficient transistor structures like FinFETs, but existing semiconductor devices still face challenges in electrical performance.
Innovation Solution
A semiconductor structure and formation method involving the patterning of a base to form discrete fins and pseudo fins, followed by the removal of pseudo fins and the thinning of isolation layers in isolation regions to balance stress and improve gate control capacity, including the use of ion implantation and wet etching to achieve target isolation layers with lower surfaces than those between discrete fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length of MOSFET is reduced to adapt to smaller feature size, then the integration density is improved, but the gate control capacity is reduced and subthreshold leakage increases
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, changing the transistor geometry from two-dimensional to three-dimensional. The gate structure wraps around the fin from multiple sides, providing enhanced control over the channel in the vertical dimension while maintaining small footprint area, thus improving integration density without sacrificing gate control capacity
Solution Approach 2:
The patent employs composite material structures including the fin body material, gate electrode materials, and isolation layer materials to optimize device performance. The combination of different materials with complementary properties enables improved electrical characteristics and gate control while maintaining scalability to smaller feature sizes
2Reliability
If isolation layers are formed to cover fin side walls, then device isolation is improved, but stress imbalance causes fin bending or tilting
Solution Approach 1:
The patent applies different properties to different parts of the isolation structure. The isolation layers have varying thicknesses in different regions - thinner near the fins to reduce stress and thicker in isolation regions for proper device isolation. This local variation in thickness prevents fin bending while maintaining isolation effectiveness
Solution Approach 2:
The patent changes the thickness parameter of isolation layers spatially to control stress distribution. By adjusting the isolation layer thickness from uniform to non-uniform, with specific regions having reduced thickness, the stress on fin structures is balanced, preventing bending or tilting while maintaining adequate isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces stress imbalance, prevents fin bending or tilting, and enhances electrical performance by improving gate control capacity and contact area between the gate structure and fin side walls.
Implementation Method 1
doping ions on the surfaces of the first mask material layers such that the etching rate of the doped first mask material layers is greater than that of the undoped first mask material layers
Implementation Method 2
a wet etching process is adopted to etch and thin the isolation layers
Data Source
AI summary
A semiconductor structure and a formation method thereof are provided. In one form, the method includes: providing a base; patterning the base to form a substrate and discrete fins and pseudo fins which protrude from the substrate, wherein the fins are located in a device region, and the pseudo fins are located in isolation regions; removing the pseudo fins in the isolation regions; forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins. Since the surfaces of the target isolation layers are lower than the surfaces of the isolation layers between the discrete fins, the volume of the target isolation layers is correspondingly reduced, and then stress generated by the target isolation layers on the fins is lowered, which causes the stress on both sides of the fins to be balanced, avoids the problem of bending or tilting of the fins in the device region in case of stress imbalance and improves the electrical performance of the semiconductor structure.