FinFET Source/Drain Junction Depths for Leakage and Performance Balance
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Solution Overview
Problem
Existing three-dimensional transistors, such as FinFETs, face challenges in simultaneously achieving low-leakage and high-performance characteristics on the same substrate, requiring innovative fabrication methods to optimize transistor regions for different electrical requirements.
Innovation Solution
The method involves forming semiconductor devices with FinFET structures by patterning fins using photolithography and self-aligned processes, creating different source/drain junction depths in various transistor regions through selective introduction of atomic or ionic species, and forming dummy gate structures to achieve optimized transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single uniform source/drain junction depth is used across the substrate, then fabrication process simplicity is maintained, but the ability to achieve both low-leakage and high-performance FETs on the same substrate is compromised
Solution Approach 1:
The substrate is divided into different transistor regions (first transistor region and second transistor region) with different source/drain junction depths. This segmentation allows each region to be optimized for specific FET types (low-leakage or high-performance) while using a unified fabrication process flow, thus achieving versatility without proportionally increasing process complexity
Solution Approach 2:
Different source/drain junction depths are implemented in different regions of the substrate according to local performance requirements. The first transistor region uses a first source/drain junction depth optimized for low-leakage FETs, while the second transistor region uses a second source/drain junction depth optimized for high-performance FETs, allowing each local area to have the quality needed for its specific function
2Reliability
If different source/drain junction depths are implemented for different transistor regions, then optimal performance for both low-leakage and high-performance FETs is achieved, but fabrication process complexity increases
Solution Approach 1:
Mask structures are formed prior to source/drain junction formation to define different regions that will receive different implantation doses. This preliminary action allows the subsequent ion implantation process to create different source/drain junction depths in different regions without requiring separate implantation steps, thus maintaining ease of manufacture while achieving optimized FET performance
Solution Approach 2:
The source/drain junction depth is varied by changing the ion implantation parameters (dose, energy, angle) for different transistor regions. By adjusting these parameters during a unified implantation process, different junction depths are achieved without adding significant fabrication complexity, thereby maintaining ease of manufacture while optimizing FET reliability
3Manufacturing precision
If uniform photolithography patterning is used across the substrate, then manufacturing simplicity is maintained, but the ability to create different fin depths for different transistor regions is compromised
Solution Approach 1:
The patterning process is segmented into multiple steps (double-patterning or multi-patterning) where different mask structures are formed for different transistor regions. This allows precise control of fin depths in first and second transistor regions separately, achieving manufacturing precision while managing patterning process complexity through systematic multi-step fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the co-optimization of transistor regions for improved performance, power, area, and cost (PPAC) requirements by enabling distinct electrical characteristics in low-leakage and high-performance regions, simplifying lithography and etching processes, and reducing manufacturing costs.
Implementation Method 1
fins are patterned using photolithography processes like double-patterning or multi-patterning
Data Source
AI summary
Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.