FinFET Gate Stack Lanthanum Diffusion and Silicon Cap Protection
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes in electronic components, challenges arise in the manufacturing of FinFETs, such as the need for precise control of gate dielectric layers and the integration of lanthanum-doped gate dielectric layers to achieve improved electrical characteristics and smaller gate dimensions, while also addressing the vulnerability of lanthanum oxide to chemical cleaning processes.
Innovation Solution
The process involves forming a gate dielectric layer, depositing a metal oxide layer, annealing to diffuse lanthanum ions into the gate dielectric layer, forming a work function layer, and using a silicon cap to protect the lanthanum-doped gate dielectric layer from chemical exposure during cleaning, ensuring improved electrical characteristics and reduced contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lanthanum-doped gate dielectric layer is formed to improve electrical characteristics, then voltage threshold matching and electrical performance are improved, but the gate dielectric layer becomes vulnerable to chemical cleaning processes
Solution Approach 1:
A silicon cap layer is deposited over the lanthanum-doped gate dielectric layer to act as a protective intermediary barrier during chemical cleaning processes. This cap prevents direct contact between the cleaning chemicals and the vulnerable lanthanum-doped gate dielectric, thereby protecting it from damage while allowing the electrical characteristics to be improved by the lanthanum doping.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent employs annealing processes to change the physical and chemical parameters of the gate dielectric layer, specifically to diffuse lanthanum ions into the gate dielectric and form a doped region. This parameter change approach allows for precise control of the gate dielectric properties even at reduced feature sizes, enabling improved electrical characteristics while maintaining manufacturability.
3Length of moving object
If gate dimensions are reduced to achieve smaller device size, then device footprint is reduced, but gap control in the gate stack becomes more challenging
Solution Approach 1:
The silicon cap layer is deposited in advance over the lanthanum-doped gate dielectric layer before subsequent processing steps. This preliminary action protects the gate dielectric structure and helps maintain precise gap control in the gate stack during manufacturing, enabling reduced gate dimensions without sacrificing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables FinFET devices with improved electrical performance, including voltage threshold matching between NMOS and PMOS devices, and allows for smaller gate dimensions with reduced gaps in the gate stack, while minimizing production costs and delays.
Implementation Method 1
annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer
Data Source
AI summary
A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.