FinFET Lateral Recess Isolation for Parasitic Capacitance Control
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Solution Overview
Problem
Short channel effects and parasitic capacitance inconsistencies in planar semiconductor devices lead to performance variability and prolonged response times, particularly in scaled-down Fin Field Effect Transistors (FinFETs), due to challenges in controlling fin height and dielectric parasitic capacitance during manufacturing.
Innovation Solution
A method involving the formation of semiconductor layers with lateral recesses and an isolation layer that fills these recesses, reducing parasitic capacitance by controlling etching depth and dielectric thickness, ensuring consistent fin height and improved uniformity, and forming gate stacks intersecting the fins to define the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fins are formed vertically on a substrate to create FinFET structures, then short channel effects are reduced and device performance is improved, but it becomes difficult to control fin height consistency across the wafer during manufacture
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the fin formation process. The mandrel serves as a pre-established template that defines the fin footprint and height, ensuring consistent fin dimensions across the wafer. The mandrel is formed at a specific depth in the substrate, and subsequent epitaxial growth of semiconductor material occurs around this predetermined structure, guaranteeing uniform fin height without requiring precise control during the fin formation step itself.
2Reliability
If dielectric material is placed between the gate and body to provide isolation, then device isolation is achieved, but parasitic capacitance increases and response time becomes too long
Solution Approach 1:
The patent applies local quality by creating a lateral recess in the fin structure at the region where the gate contacts the body. This recess removes or reduces dielectric material specifically at the critical interface between gate and body, minimizing parasitic capacitance where it has the most impact on response time. The recess is formed selectively in this localized area while maintaining dielectric isolation in other regions, thus achieving a balance between isolation and speed.
3Reliability
If the fin height is increased to improve device performance, then short channel effects are reduced, but parasitic capacitance at the bottom of the fin increases
Solution Approach 1:
The patent applies segmentation by dividing the fin structure into distinct regions: an upper portion with full height for channel formation and a lower portion with a lateral recess. This segmentation allows the fin to maintain sufficient height for good short channel effect control in the channel region, while the recessed lower portion reduces the area of dielectric contact and thus minimizes parasitic capacitance. The mandrel structure enables this segmented geometry to be formed with precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of fin height and reduces parasitic capacitance, leading to improved performance consistency and faster response times in semiconductor devices by controlling the etching depth and dielectric layer thickness, thus addressing the challenges of short channel effects and parasitic capacitance.
Implementation Method 1
a parasitic capacitance is formed at the bottom of the fin due to dielectric between the gate and the body
Implementation Method 2
selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess
Data Source
AI summary
A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.