FinFET Device Lattice Mismatch and Graded Buffer Solution
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Solution Overview
Problem
The integration of alternative semiconductor materials with silicon substrates in FinFET devices is hindered by lattice constant mismatches, leading to defects and limited formation of stable, fully-strained layers, which complicates the manufacturing of high-performance FinFET devices for CMOS technology.
Innovation Solution
The method involves forming fins with different semiconductor materials for PMOS and NMOS FinFET devices, using a substrate material for the lower portion and a different semiconductor material for the upper portion, and applying a semiconductor material cladding on the exposed upper portion, allowing for the formation of fully-strained, defect-free layers through epitaxial growth and recess etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative semiconductor materials are integrated with silicon substrates in FinFET devices, then device performance is improved, but lattice constant mismatches cause defects and limit the formation of stable layers
Solution Approach 1:
The patent introduces a graded buffer layer as an intermediary between the silicon substrate and the alternative semiconductor material. This buffer layer has a composition that gradually transitions from pure silicon to the alternative material, reducing the lattice constant mismatch and enabling the formation of stable, defect-free channels while maintaining improved device performance
Solution Approach 2:
The patent changes the compositional parameter of the buffer layer, creating a graded structure where the material composition varies continuously from the substrate interface to the channel interface. This parameter change allows the lattice constant to transition smoothly, reducing defects while preserving the performance benefits of alternative semiconductor materials
2Reliability
If separate SRB layers are formed for NMOS and PMOS devices, then material optimization is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent creates a universal graded buffer layer structure that can serve both NMOS and PMOS devices. By forming a single graded buffer that accommodates both device types, the patent eliminates the need for separate SRB layers while still providing material optimization for each device type through selective epitaxial growth in different regions
Solution Approach 2:
The patent merges the formation of separate SRB layers into a single unified graded buffer structure. This combined approach reduces manufacturing steps and process complexity while maintaining the ability to optimize materials for both NMOS and PMOS devices through subsequent selective processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of FinFET devices with enhanced performance characteristics, including improved drive current and reduced leakage current, while simplifying the manufacturing process by reducing the need for separate SRB layers for NMOS and PMOS devices.
Implementation Method 1
forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device
Implementation Method 2
recess etching processes
Data Source
AI summary
One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device.