FinFET Layout Verification via Device Code Extraction
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Solution Overview
Problem
Current semiconductor layout verification methods require excessive information to express device layouts, making efficient design, analysis, and verification challenging due to the use of numerous parameters.
Innovation Solution
A method and system for simplifying layout parameters by extracting device codes based on gate line units, including active regions and silicon fins, and synthesizing these codes into a code stream for efficient layout design and verification, allowing for conversion between layout and schematic parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional layout verification methods use numerous parameters to express device layouts, then comprehensive layout information is captured, but the complexity of design, analysis, and verification increases significantly
Solution Approach 1:
The patent extracts only the essential geometric features from complex layout data - specifically gate line positions and silicon fin intersecting points - to create a simplified device code representation. This extraction process removes unnecessary detailed information while retaining the critical geometric characteristics needed for verification, thereby reducing system complexity without significant loss of functional layout information.
Solution Approach 2:
The patent transforms the representation parameters from numerous continuous geometric parameters (coordinates, dimensions, shapes) to a discrete code system where devices are represented by integer codes based on gate line indices and fin intersection counts. This parameter transformation simplifies the data structure and reduces computational complexity while preserving the essential geometric relationships needed for layout verification.
2Measurement precision
If detailed geometric parameters are used to represent each device in the layout, then precise device characteristics are maintained, but the number of bits required to represent layout information increases
Solution Approach 1:
The patent creates a simplified code copy of the geometric information rather than storing the full geometric data. Each device is represented by a device code that copies only the essential identifying features (gate line index and fin intersection count) instead of the complete geometric description, significantly reducing data volume while maintaining sufficient precision for verification purposes.
Solution Approach 2:
The patent segments the device representation into discrete, countable features - specifically the gate line index and the number of silicon fin intersections - rather than storing continuous geometric parameters. This segmentation allows precise device identification using integer codes, reducing the data volume from continuous floating-point coordinates to discrete integer values that require fewer bits to represent.
3Reliability
If comprehensive layout parameters are extracted for verification, then accurate layout vs. schematic verification is achieved, but the processing time and computational resources increase
Solution Approach 1:
The patent changes the parameter representation from complex continuous geometric data to simple discrete integer codes. This parameter transformation enables faster computational operations during verification, as comparing and processing integer codes is significantly more efficient than manipulating detailed geometric coordinates and dimensions, thereby reducing processing time while maintaining verification accuracy.
Solution Approach 2:
The patent extracts only the critical geometric features needed for verification - gate line positions and fin intersection points - and represents them in a simplified code format. This extraction eliminates unnecessary detailed geometric information that would require extensive processing, thereby reducing computational resources and processing time while retaining the essential features needed for accurate layout verification.
Data Source
AI summary
There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.