FinFET Layout Design System for Short Channel Effect Control
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Solution Overview
Problem
Increasing integration density in semiconductor devices leads to short channel effects, necessitating the development of transistors that operate effectively at low power with high speeds, which existing technologies struggle to achieve.
Innovation Solution
A layout design system and method for fabricating finFETs, involving a processor, storage module, and correction module to adjust dummy design widths, resulting in active fins with varying widths and hard mask layers that allow for efficient gate structure formation, enabling transistors with different characteristics and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased, then device capacity and speed are improved, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional finFET structures with vertical channels. The fin structures extend upward from the substrate, creating a 3D configuration where the channel flows vertically through the fin. This dimensional change provides better gate control over the channel while maintaining high integration density, effectively suppressing short channel effects that plague conventional planar transistors at scaled dimensions
Solution Approach 2:
The patent segments the channel into multiple parallel fin structures rather than using a single large planar channel. Each fin acts as an independent channel segment with its own gate control. This segmentation allows each fin to maintain effective gate control despite the overall high integration density, preventing short channel effects while achieving high device capacity through the combined effect of multiple fins
2Adaptability or versatility
If dummy structure widths are varied, then transistor characteristics are optimized, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by varying the widths of dummy structures at specific locations to achieve desired transistor characteristics. Different dummy structure widths are placed in different regions to control threshold voltages and leakage currents locally. This allows optimization of transistor performance in specific areas without requiring complex manufacturing processes, as the width variations are implemented through standard photolithography patterning
Solution Approach 2:
The patent changes the width parameter of dummy structures to control transistor characteristics. By adjusting the width of dummy structures adjacent to active fins, the patent controls the effective channel width, threshold voltage, and leakage current of the resulting transistors. This parameter change approach enables flexible device optimization while maintaining compatibility with existing manufacturing processes
Data Source
AI summary
A layout design system for designing a semiconductor device includes a processor, a storage module storing an intermediate design, and a correction module used by the processor to correct the intermediate design. The intermediate design includes an active region and dummy designs on the active region. Each dummy design includes a dummy structure and dummy spacers disposed at opposite sides of the dummy structure. The correction module is configured to alter widths of regions of at least some of the dummy designs. The corrected design is used to produce a semiconductor device having an active fin, a hard mask layer disposed on the active fin, a gate structure crossing the over the hard mask layer, and a spacer disposed on at least one side of the gate structure. The hard mask layer, and the active fin, are provided with widths that vary due to the dummy designs.