FinFET Cell Layout Using Digital Rules for Higher Electromigration Current
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Solution Overview
Problem
As electronic circuits are designed to operate at higher speeds, existing design methods using analog circuit rules and analog fin boundaries face limitations in performance improvements due to device size constraints.
Innovation Solution
The use of a combination of analog and digital circuit design rules, specifically integrating digital circuit design rules with a digital fin boundary, to design and manufacture semiconductor structures, allowing for increased trans-conductance, unit gain frequency, and electromigration current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog circuit design rules with analog fin boundary are used, then device performance (trans-conductance, unit gain frequency) is improved, but device size increases and operating speed is limited
Solution Approach 1:
The patent changes the fundamental design rule parameters from analog to digital, including fin boundary definition, metal layer thickness, and spacing rules. This parameter transformation allows digital circuits to achieve higher operating speeds (28-448 Gbps) while maintaining adequate performance through optimized digital-specific parameters like larger contact poly pitch and wider metal over diffusion
Solution Approach 2:
Instead of continuing to scale down analog circuits to improve speed, the patent inverts the approach by applying digital circuit design rules to high-speed analog circuits. This inversion uses larger feature sizes (wider metal lines, larger vias) characteristic of digital design to achieve high-speed performance, breaking the traditional constraint that high performance requires small device sizes
2Productivity
If device size is reduced to improve integration density, then manufacturing precision requirements increase, but this limits the ability to increase key device parameters for high-speed operation
Solution Approach 1:
The patent changes the size parameters entirely by adopting digital design rules with larger minimum feature sizes. This allows manufacturing with relaxed precision requirements while achieving high integration density through efficient digital layout techniques and optimized cell designs that maximize space utilization with the larger digital geometry
3Reliability
If larger metal structures are used to increase trans-conductance and reduce resistance, then device area increases, but this conflicts with the goal of high-speed operation at scaled dimensions
Solution Approach 1:
The patent changes the metal structure parameters by adopting digital design rules that specify wider metal lines, larger vias, and increased metal over diffusion. These parameter changes reduce resistance and increase trans-conductance while the overall device area is controlled through efficient digital cell layout and compact standard cell designs
Solution Approach 2:
The patent creates a universal digital design rule set that serves multiple functions: it defines fin boundary, metal layer dimensions, spacing requirements, and interconnect structures. This universal digital framework enables high-speed operation, adequate trans-conductance, and compact integration all through a single design rule methodology rather than separate analog optimizations
Data Source
AI summary
An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.