FinFET Cell Layout Using Well Tap Stripes for Latch-Up Control
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Solution Overview
Problem
Integrated circuits face challenges in efficiently laying out cells to enhance reliability due to area consumption by components like power lines, shielding, and decoupling capacitors, which reduces performance without expanding the floorplan dimensions.
Innovation Solution
Implementing well tap cells with high-dopant regions and transistor gate stripes to prevent transistor latch-up and improve signal integrity, using implant layers and ESD transistors to manage capacitance and connectivity, while optimizing layout to balance latch-up prevention and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If well tap cells with high-dopant regions and transistor gate stripes are added to prevent transistor latch-up, then reliability is improved, but area consumption increases
Solution Approach 1:
The patent merges the latch-up prevention function with the existing transistor gate structure by integrating well tap cells that utilize the same gate stripe infrastructure. The well tap cells are formed within existing transistor regions, combining the protective function with the existing circuit architecture rather than adding completely separate structures.
Solution Approach 2:
The patent applies local quality by selectively forming well tap cells only in specific regions where latch-up is susceptible, rather than uniformly across the entire chip. The design tools identify critical regions and place well tap cells only where needed, optimizing the balance between reliability improvement and area consumption.
2Reliability
If decoupling capacitors and shielding structures are added to improve signal integrity, then signal integrity is improved, but area consumption increases
Solution Approach 1:
The patent makes the transistor gate stripes serve multiple functions: they act as both the gate electrode for transistor operation and as capacitance structures for signal integrity enhancement. The gate stripes provide both transistor control and decoupling capacitance, eliminating the need for separate dedicated components.
Solution Approach 2:
The patent combines the signal integrity enhancement function with the existing transistor gate structure. The well tap cells with gate stripes provide both latch-up prevention and signal integrity improvement simultaneously, merging multiple protective functions into a single integrated structure.
3Ease of operation
If power lines and routing structures are expanded to accommodate all components, then connectivity is improved, but floorplan dimensions must be expanded
Solution Approach 1:
The patent nests the well tap cells within the existing transistor regions and routing infrastructure. The additional protective structures are embedded within the existing layout rather than requiring external expansion, allowing multiple functions to share the same spatial envelope.
Data Source
AI summary
Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.