FinFET Layout Conversion Using Mandrel Spacing and Connectors
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Solution Overview
Problem
Converting older planar structure layouts to FinFET layouts is a resource-intensive process due to different design rules, making it costly and inefficient to reuse photomasks and maximize fin density within existing planar transistor structures.
Innovation Solution
A method involving the use of elongate mandrels and spacers to form FinFETs within the confines of planar structures, where mandrels are placed with specified pitches and orientations to maximize fin density, and connective elements are added to address misalignment and spacing issues, allowing for automatic conversion of planar layouts to FinFET layouts using a layout generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar structure layouts are manually converted to FinFET layouts, then FinFET device performance is improved, but conversion cost and time increase significantly
Solution Approach 1:
The patent uses a layout generator to automatically copy and adapt planar device layouts into FinFET layouts, eliminating manual conversion. The system reads planar layout data and generates corresponding FinFET layouts with proper fin structures, mandrels, and spacers, dramatically reducing conversion time while maintaining design integrity.
Solution Approach 2:
The patent replaces the manual mechanical conversion process with an automated computer-based layout generator. The system uses software algorithms to automatically transform planar layout coordinates and structures into FinFET layouts, substituting human manual work with automated computational processes.
2Manufacturing precision
If additional photomasks are created for FinFET conversion, then layout conversion accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes existing photomasks serve multiple functions by designing the layout conversion process to reuse original planar photomask patterns where possible. The layout generator identifies opportunities to use existing photomasks for both planar and FinFET structures, reducing the need for additional mask fabrication.
Solution Approach 2:
The patent changes layout parameters such as fin pitch, mandrel dimensions, and spacer thicknesses to optimize fin density while maintaining compatibility with existing photomask sets. The layout generator adjusts these parameters automatically to achieve high conversion accuracy without requiring new masks.
3Productivity
If fin density is maximized within planar structures, then device performance is improved, but layout complexity increases
Solution Approach 1:
The patent segments the layout conversion process into distinct automated steps: reading planar layout data, generating fin structures, placing mandrels, adding spacers, and verifying constraints. The layout generator handles each segment automatically, managing complexity through systematic decomposition of the conversion process.
Solution Approach 2:
The layout generator acts as an intermediary between planar layout designers and FinFET manufacturing processes. It automatically translates high-level planar design intent into detailed FinFET layouts with optimized fin density, mediating the complexity transformation without requiring manual intervention at each detailed design step.
Data Source
AI summary
A semiconductor manufacturing method of generating a layout for a device includes defining a first plurality of mandrels in a first active region of a first layout. Each mandrel of the first plurality of mandrels extends in a first direction and being spaced apart in a second direction perpendicular to the first direction. The method further includes defining a second plurality of mandrels in a second active region of the first layout. Each mandrel of the second plurality of mandrels extends in the first direction and being spaced apart in the second direction. An edge of the first active region is spaced from an edge of the second active region by a minimum distance less than a specified minimum spacing. The method further includes connecting, using a layout generator, at least one mandrel of the first plurality of mandrels to a corresponding mandrel of the second plurality of mandrels.