FinFET Layout Pattern Generation with Variable Stripe Spacing
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Solution Overview
Problem
Conventional methods for generating FinFET layout patterns are limited by the use of sacrificial layers with uniform spacing and width, restricting the design of semiconductor devices and the available substrate area due to the inability to create patterns with unequal spacings and widths.
Innovation Solution
A method involving the generation of layout patterns with sub-patterns having pitches in simple integer ratios, where first and second stripe patterns are created with aligned edges and differing widths and spacings, allowing for unequal spacings and widths in the final pattern, which is then transferred to a photomask and used in a photolithographic and etching process to form patterned structures on a substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sacrificial layers are distributed with the same spacing and width, then the fabrication process is simple and easy to manufacture, but the design flexibility and available substrate area are restricted
Solution Approach 1:
The layout pattern is segmented into multiple sub-patterns with different spacing and width characteristics. The computer system calculates and generates first stripe patterns with first spacing and first width, and second stripe patterns with second spacing and second width, allowing different regions to have different geometric parameters while maintaining manufacturability through systematic classification.
Solution Approach 2:
Different regions of the substrate are assigned different local qualities in terms of spacing and width parameters. The method allows first sub-patterns to have different spacing and width characteristics from second sub-patterns, enabling optimized local design flexibility in different areas of the circuit layout while maintaining overall process simplicity.
2Ease of manufacture
If sacrificial layers are distributed with the same spacing and width, then the manufacturing process is straightforward, but the available substrate area is reduced due to redundancy
Solution Approach 1:
The method systematically changes the geometric parameters of stripe patterns by classifying them into different groups with different spacing and width values. The computer system calculates optimal parameter combinations that reduce redundancy in shallow trench isolation structures while maintaining straightforward manufacturing processes through standardized pattern generation.
3Ease of manufacture
If uniform spacing and width are used for sacrificial layers, then the fabrication process is simple, but precise semiconductor device placement cannot be achieved
Solution Approach 1:
The computer system performs preliminary calculation and classification of layout patterns into multiple sub-patterns with different spacing and width parameters before the actual fabrication process. This preliminary action enables precise device placement to be achieved while maintaining fabrication simplicity, as the optimized pattern parameters are predetermined and systematically organized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of patterned structures with reduced redundancy in shallow trench isolation structures, allowing for more efficient use of substrate area and precise semiconductor device placement, even with variations in spacing, thereby enhancing the applicability of semiconductor devices.
Implementation Method 1
transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process
Implementation Method 2
Through the etching process, the pattern defined by the spacers can be transferred into the underneath substrate
Data Source
AI summary
A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.