FinFET LDMOS Drift Region Impurity Control for High-Frequency Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high frequency operations while maintaining integration density and reducing device size, particularly in the design of multigate transistors for high-frequency communications.
Innovation Solution
The semiconductor device incorporates a FinFET structure with a laterally double diffused metal-oxide-semiconductor (LDMOS) transistor design, featuring active fins, a gate structure that crosses over these fins, and an embedded insulating layer to control operating voltage and breakdown voltage, along with distinct impurity concentrations in source and drain regions to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multigate transistors are used to increase integration density, then integration density is improved, but device size increases
Solution Approach 1:
The patent employs FinFET structures with vertical fins extending from the substrate, transforming the traditional planar two-dimensional channel into a three-dimensional vertical channel. This dimensional change allows multiple gates to wrap around the fin structure, achieving multigate control and higher integration density without proportionally increasing the device footprint on the substrate surface.
2Speed
If LDMOS transistor design is used for high frequency operations, then frequency response is improved, but device complexity increases
Solution Approach 1:
The patent merges the LDMOS transistor design with FinFET structure, combining the advantages of both architectures. The LDMOS characteristics provide rapid switching response and high-frequency performance, while the FinFET structure offers superior gate control and scaling capability. The merged structure integrates drift regions, source regions, and gate structures that cross over active fins, achieving high-frequency operations with improved integration density.
3Reliability
If gate structure overlaps drift region, then voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements local quality by creating distinct regions with different impurity concentrations and structural characteristics. The drift region has a first impurity concentration while the drain region has a second impurity concentration higher than the first. The gate structure is positioned to overlap specific portions of the drift region in plan view, providing localized voltage control and electric field management where needed, while maintaining manufacturing feasibility through defined regional characteristics.
Data Source
AI summary
A semiconductor device may include an active fin, an element isolation film on a lower portion of the active fin and a gate structure crossing over the active fin. The gate structure may include first and second sides. The device may also include a source region and a drift region adjacent the first and second sides of the gate structure, respectively. The drift region may have a first impurity concentration. The device may further include a drain region that is in the drift region and may have a second impurity concentration higher than the first impurity concentration, a first trench that is in the drift region and may have a depth less than a height of the active fin, and an upper embedded insulating layer in the first trench. The gate structure may overlap a portion of the drift region and a portion of the first trench.