FinFET LDMOS Dummy Gate Segmentation for CMP Dishing

Solution Overview

Problem

Conventional LDMOS devices face challenges in achieving breakdown voltages greater than 10V due to dishing effects in the CMP process and micro-loading effects in epitaxial growth, especially with shrinking device sizes, where STI structures are not conducive to FinFET devices under the 14 nm technology node.

Innovation Solution

Incorporating dummy gate structures between the gate and drain regions, which reduce CMP dishing and micro-loading effects in epitaxial growth, with a density of 5 to 30% and lengths between 0.01 to 0.1 um, to maintain adequate breakdown voltage without overlapping the second doped region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate length is increased to ensure breakdown voltage greater than 10V, then breakdown voltage is improved, but dishing problems in the CMP process worsen

Engineering Contradiction:

Improvebreakdown voltageVSAvoidCMP dishing

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure is segmented into a real gate portion and dummy gate portions. The dummy gate portions are distributed in the second doped region to a density of 5 to 30%, breaking up the continuous structure that causes dishing. This segmentation maintains the effective gate length for breakdown voltage while creating smaller, distributed features that reduce CMP dishing effects.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Dummy gate structures serve as intermediary elements between the real gate and the drain region. These dummy gates act as buffer structures that absorb the mechanical stress and material removal variations during CMP processing, protecting the functional gate-length determination from dishing effects while maintaining the necessary breakdown voltage characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If STI structures are introduced in the active region between gate and drain to achieve breakdown voltage greater than 10V, then breakdown voltage is improved, but compatibility with FinFET devices under 14 nm technology node worsens

Engineering Contradiction:

Improvebreakdown voltageVSAvoidcompatibility with FinFET devices

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The dummy gate structures provide multiple functions: they extend the effective gate length for breakdown voltage control, serves as spacing elements from the drain, and maintain compatibility with both planar and FinFET device architectures. This multi-functional approach allows the same structure to work across different device types and technology nodes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The dummy gates are placed specifically in the second doped region between the gate and drain, creating local structural modifications only where needed. This localized approach maintains the breakdown voltage in the critical region while preserving the overall device architecture compatibility with advanced FinFET processes.

Inventive Principle:

Principle #3Local quality

3Productivity

If device size is shrunk, then integration density is improved, but micro-loading effects in the epitaxial growth process worsen

Engineering Contradiction:

Improveintegration densityVSAvoidmicro-loading effects

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The gate structure is segmented into a real gate portion and dummy gate portions. The dummy gate portions are distributed in the second doped region to a density of 5 to 30%, breaking up the continuous structure that causes dishing. This segmentation maintains the effective gate length for breakdown voltage while creating smaller, distributed features that reduce CMP dishing effects.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Dummy gate structures serve as intermediary elements between the real gate and the drain region. These dummy gates act as buffer structures that absorb the mechanical stress and material removal variations during CMP processing, protecting the functional gate-length determination from dishing effects while maintaining the necessary breakdown voltage characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9570606B2FinFET LDMOS device and manufacturing methods

Publication Date: 2017.02.14 SEMICON MFG INT (SHANGHAI) CORP

AI summary

An LDMOS (Laterally-Diffused Metal Oxide Semiconductor) device has a substrate, which includes a first doped region, a second doped region, and a shallow trench isolation (STI) region disposed in the second doped region. The first doped region and the second doped region are adjacent and have different conductivity types. The device also has a gate structure disposed on the substrate; the gate structure substantially does not overlap the second doped region.