FinFET Fin Layout With Level Isolation to Limit Leakage Current
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Solution Overview
Problem
Existing FinFET device fabrication technologies face issues with leakage current due to unlevel isolation regions between fins, leading to inconsistent processing and performance.
Innovation Solution
Forming isolation regions with a level surface across different portions to ensure the gate structure lands uniformly, which reduces leakage current by allowing fins to bend towards each other, creating a consistent and stable environment for subsequent processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation regions are formed between fins, then the fins are isolated from each other, but the isolation regions become unlevel causing leakage current and inconsistent processing
Solution Approach 1:
The method performs preliminary planarization by forming a first dummy fin structure before the actual fins, then uses this dummy structure as a reference to form isolation regions at a first level. Subsequently, the dummy fin is removed and second dummy fin structures are formed to adjust the isolation regions to a second level, ensuring levelness before final fin formation. This preliminary action sequence prevents leakage current by establishing level isolation regions upfront.
Solution Approach 2:
Dummy fin structures serve as intermediary elements during the fabrication process. These dummy fins are formed temporarily to define isolation region levels, then removed after serving their purpose. The dummy structures act as mediators that enable precise isolation region formation without directly becoming part of the final device, resolving the contradiction between isolation effectiveness and levelness.
2Productivity
If the gate structure is formed over unlevel isolation regions, then the fabrication process can proceed, but leakage current increases due to inconsistent gate landing
Solution Approach 1:
The method performs preliminary planarization steps by forming isolation regions at multiple levels using dummy fin structures before the actual gate formation. The isolation regions are adjusted to a second level that ensures level gate landing. This preliminary action sequence maintains fabrication process continuity while preventing leakage current by establishing level isolation regions upfront, eliminating the need for rework or process interruptions.
3Productivity
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated, but manufacturing precision and process consistency become more difficult to maintain
Solution Approach 1:
The method performs preliminary planarization by forming isolation regions at controlled levels using dummy fin structures before the actual fins are formed. This preliminary establishment of level isolation regions provides a stable foundation for subsequent gate and fin formation, maintaining manufacturing precision even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The method changes the physical state and dimensions of dummy fin structures through multiple formation and removal cycles. The dummy fins are formed with specific dimensions, used to define isolation region levels, then removed. This parameter manipulation of temporary structures enables precise control of isolation region geometry, maintaining manufacturing precision at smaller feature sizes.
Data Source
AI summary
A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.