FinFET Semiconductor Liner Strain Delivery
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Solution Overview
Problem
In the semiconductor industry, achieving enhanced carrier mobility in FinFETs is challenging due to difficulties in delivering a given amount of strain into the channel region, leading to device instability and potential failure.
Innovation Solution
A semiconductor liner is formed by epi-growing a second semiconductor material with a greater lattice constant than the first material, adjoining the lower portion of the fin structure, and performing an oxidation process to create notches that extend into the middle portion, thereby delivering strain into the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained materials are used in source/drain portions to enhance carrier mobility, then carrier mobility is improved, but it is difficult to deliver a given amount of strain into the channel region, leading to device instability and failure
Solution Approach 1:
The fin structure is divided into multiple portions: a channel portion, a first source/drain portion, and a second source/drain portion. The semiconductor liner is selectively positioned on the outer sidewalls of the first source/drain portion and the second source/drain portion, but not on the channel portion. This segmentation allows strain to be delivered to the source/drain regions without compromising the channel integrity, thereby improving carrier mobility while maintaining device stability.
Solution Approach 2:
The semiconductor liner is applied locally to specific regions (outer sidewalls of source/drain portions) rather than uniformly across the entire fin structure. This local quality approach enables precise control over where strain is introduced, delivering the required strain to the channel region through the source/drain portions while avoiding unwanted strain in other areas, thus resolving the contradiction between strain delivery precision and device stability.
2Reliability
If a semiconductor liner is formed by epi-growing a second semiconductor material with a greater lattice constant, then strain is delivered into the channel region enhancing carrier mobility, but the lattice mismatch may cause dislocation and reduce device reliability
Solution Approach 1:
The semiconductor liner with greater lattice constant is applied locally only to the outer sidewalls of the source/drain portions, avoiding the channel portion. This localized application allows the lattice-mismatched material to deliver strain to the channel region through the source/drain portions without creating dislocations in the channel itself, thereby maintaining both carrier mobility enhancement and lattice structure stability.
Solution Approach 2:
The first source/drain portion and the second source/drain portion act as intermediaries between the semiconductor liner and the channel portion. The liner is positioned on the outer sidewalls of these source/drain portions, which then transmit the strain into the channel region indirectly. This intermediary approach allows strain delivery while preventing direct lattice mismatch at the channel, reducing dislocation risk and maintaining device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and reduces the likelihood of device failure by achieving desired device performance characteristics such as saturation current.
Implementation Method 1
a second semiconductor material is epi-grown covering the fin structure, wherein the second semiconductor material has a second lattice constant greater than the first lattice constant
Implementation Method 2
performing an oxidation process to the second portion of the second semiconductor material to form a pair of notches extending into opposite sides of the middle portion
Data Source
AI summary
The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant.