FinFET Composite Liner Surface Conversion Against Crystallization

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Solution Overview

Problem

The crystallization of amorphous silicon liners in FinFET devices during thermal processes leads to defects and constraints on low-temperature processing, affecting yield and critical dimension stability.

Innovation Solution

A surface treatment process converts an upper layer of the amorphous silicon liner into a dielectric conversion layer, such as oxide or nitride, using oxygen or ammonia-containing gases/plasma, preventing crystallization and allowing higher-temperature thermal processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If amorphous silicon liner is used in FinFET devices, then low-temperature processing is enabled, but crystallization during thermal processes causes defects and yield loss

Engineering Contradiction:
Improveprocessing temperatureVSAvoidyield
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

A surface treatment process is performed on the amorphous silicon liner before subsequent thermal processing to convert the outer surface into a dielectric layer (oxide or nitride). This preliminary conversion prevents crystallization during later high-temperature steps, enabling the use of higher processing temperatures without causing defects or yield loss.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If amorphous silicon liner is used, then processing flexibility is improved, but critical dimension stability deteriorates due to crystallization

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidcritical dimension stability
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The surface treatment process is applied in advance to convert the liner surface into a stable dielectric layer, preventing subsequent crystallization that would compromise critical dimension stability. This allows flexible thermal processing while maintaining precise dimensional control.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If high-temperature thermal processes are performed, then processing options are expanded, but liner crystallization occurs causing defects

Engineering Contradiction:
Improveprocessing optionsVSAvoidliner crystallization defects
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The amorphous silicon liner undergoes a surface treatment process before high-temperature processing to convert its outer surface into a thermally stable dielectric layer. This preliminary conversion eliminates the harmful crystallization effect during subsequent high-temperature steps, enabling expanded processing options without generating defects.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The surface treatment process changes the physical and chemical parameters of the liner surface, transforming it from amorphous silicon to a dielectric material with different thermal stability characteristics. This parameter change enables the liner to withstand high-temperature processing without crystallization.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances yield and maintains critical dimension stability by preventing liner crystallization, enabling wider processing choices and improved protection of semiconductor fins.

Implementation Method 1

A surface treatment process converts an upper layer of the amorphous silicon liner into a conversion layer, such as oxide or nitride

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

using oxygen or ammonia-containing gases/plasma

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS20260052724A1Fin field-effect transistor device with composite liner for the fin
Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260052724A1 patent drawing
  • US20260052724A1 patent drawing
  • US20260052724A1 patent drawing

AI summary

A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a liner over the fin; performing a surface treatment process to convert an upper layer of the liner distal to the fin into a conversion layer, the conversion layer comprising an oxide or a nitride of the liner; forming isolation regions on opposing sides of the fin after the surface treatment process; forming a gate dielectric over the conversion layer after forming the isolation regions; and forming a gate electrode over the fin and over the gate dielectric.