FinFET Logic-SRAM Layout for Leakage and Cell Scaling
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Solution Overview
Problem
Existing semiconductor manufacturing techniques face challenges in optimizing both logic device performance and SRAM cell design, particularly in achieving high speed and low power consumption while managing issues like leakage, latch-up, and fin width requirements for FinFET devices.
Innovation Solution
The approach involves co-optimizing FinFET devices for logic and SRAM applications by adjusting fin dimensions, gate lengths, and well isolation spaces to balance performance and power consumption, using structures like single fin and multi-fin configurations, and varying end-cap lengths to improve contact resistance and leakage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET fin critical dimension is reduced to improve logic device performance, then switching performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct regions with different fin structures. The semiconductor device includes a first region with logic devices having fins of a first critical dimension and a second region with SRAM devices having fins of a second critical dimension. This segmentation allows independent optimization of each region's fin dimensions without requiring complex multi-step patterning processes, as the different fin dimensions are established through selective fin formation in different regions.
2Area of stationary object
If SRAM cell size is reduced to improve cell density, then cell scaling is improved, but leakage and latch-up issues worsen
Solution Approach 1:
The patent applies local quality by implementing different fin critical dimensions specifically for SRAM devices compared to logic devices. SRAM device fins have a second critical dimension that is different from the first critical dimension of logic device fins, allowing optimization of SRAM cell characteristics including leakage and latch-up performance while maintaining compact cell size. This local differentiation enables SRAM cells to achieve small footprint without suffering from excessive leakage or latch-up issues.
Data Source
AI summary
Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.