FinFET Gate Spacer Structure With Protected Low-k Source/Drain Interface
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, continue to shrink in feature size, the capacitance between the gate and source/drain regions increases, leading to performance issues and potential damage to the source/drain regions during the formation of low-k spacers.
Innovation Solution
The use of epitaxial source/drain regions and the formation of low-k spacers, protected by a protection layer, to reduce capacitance between the gate and source/drain regions without damaging the source/drain regions, utilizing a combination of materials like silicon oxycarbonitride and air gaps to lower the k-value of the spacer material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k spacers are formed to reduce capacitance, then capacitance between gate and source/drain regions is reduced, but source/drain regions may be damaged during the formation process
Solution Approach 1:
A protection layer is introduced as an intermediary between the low-k spacer formation process and the source/drain regions. This protection layer acts as a mediator that allows the low-k spacer to be formed while preventing direct contact and potential damage to the source/drain regions, thus resolving the contradiction between achieving capacitance reduction and preventing damage.
Solution Approach 2:
The protection layer is formed in advance before the low-k spacer material is deposited. This preliminary action ensures that the source/drain regions are protected before any potentially harmful processes occur, allowing the subsequent low-k spacer formation to proceed without risking damage to the sensitive source/drain regions.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but capacitance between gate and source/drain regions increases
Solution Approach 1:
The dielectric constant (k-value) of the spacer material is changed from a conventional higher-k material to a low-k material. This parameter change allows the spacer to provide better electrical isolation between the gate and source/drain regions, thereby reducing capacitance even as feature sizes are reduced to increase integration density.
Solution Approach 2:
The patent employs a composite structure combining the low-k spacer material with the protection layer. This composite approach allows the low-k spacer to reduce capacitance while the protection layer prevents damage, enabling continued scaling to higher integration densities without sacrificing reliability.
Data Source
AI summary
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.