FinFET Fin Patterning via Mandrel Modification

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing fin structures for FinFETs with critical dimensions below 20 nm, as direct optical lithography struggles to form such small patterns, leading to issues like insufficient bottom separation and etching residue due to narrow fin spaces.

Innovation Solution

The method involves modifying mandrel patterns by adjusting the spaces and widths between active and dummy fin patterns, using a computer-aided design system to create a photo mask that expands the space between adjacent fin structures, facilitating easier patterning and reducing residue through the introduction of dummy fin patterns and adjusted mandrel patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If direct optical lithography is used to form fin structures with critical dimensions below 20 nm, then manufacturing process simplicity is maintained, but patterning precision and fin structure quality deteriorate due to insufficient bottom separation and etching residue

Engineering Contradiction:
Improvefin structure patterning precisionVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple stages: first forming mandrel patterns with relaxed pitch, then using spacer deposition to define the final fin patterns. This segmentation allows each stage to be optimized independently, achieving sub-20nm precision without requiring direct high-resolution lithography.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mandrel patterns are formed in advance with larger dimensions that are easier to pattern using optical lithography. These preliminary mandrels serve as templates for the final fin structures, allowing the actual fin patterning to be defined by spacer thickness rather than direct lithography.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If space between adjacent fin structures is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to insufficient bottom separation and etching residue

Engineering Contradiction:
Improvedevice densityVSAvoidfin etching quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Spacer materials are deposited as intermediary layers between the mandrel patterns and the final fin structures. These spacers provide physical separation and define the fin pitch through their thickness, enabling precise control of fin spacing while maintaining adequate etch access for bottom separation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The pitch control is shifted from the lateral dimension (where lithography resolution is limiting) to the vertical dimension (where thin film deposition thickness can be precisely controlled). This dimensional transition enables sub-20nm fin pitch while maintaining manufacturing precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If mandrel pattern pitch is reduced to form closer fin structures, then device density is improved, but ease of manufacture deteriorates due to difficulty in patterning and increased residue

Engineering Contradiction:
Improvefin structure densityVSAvoidpatterning ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The mandrel patterns serve as copies or templates that define the positions of the final fin structures. The actual fin patterns are copied from the mandrel geometry through spacer formation, allowing the mandrels to be formed at relaxed pitch while achieving higher density fins through the spacer multiplication effect.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20230260796A1Method of manufacturing semiconductor devices
Publication Date: 2023.08.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230260796A1 patent drawing
  • US20230260796A1 patent drawing
  • US20230260796A1 patent drawing

AI summary

In a method of manufacturing a semiconductor device, an initial pattern layout is obtained. The initial pattern layout incudes fin patterns which include active fin patterns to be formed as active fin structures and dummy fin patterns not to be formed as actual fin structures or to be removed. The locations of the fin patterns are modified, as follows. A space between adjacent active fin patterns is increased by a first amount, a space between the dummy fin patterns is decreased by a second amount, and a space between one of the dummy fin patterns and one of the active fin patterns adjacent to the one of the dummy fin patterns is decreased by a third amount. Mandrel patterns are placed so that the fin patterns of which locations are modified are placed along longitudinal edges of the mandrel patterns.