FinFET Fabrication Using Mask-less Etching and Thermal Annealing
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Solution Overview
Problem
FinFETs face challenges with reduced gate control over the channel due to shrinking channel lengths, leading to short-channel effects and subthreshold leakage, as well as non-uniform dopant distribution affecting threshold voltage and device performance, particularly in SRAM devices.
Innovation Solution
A method for fabricating FinFET structures involving the formation of super step retrograde wells by doping and thermal annealing, which enhances gate control and dopant distribution, including the use of mask-less etching and dielectric layer formation to improve sidewall spacer integration and prevent interface reactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is continuously decreased to increase integration level and switch speed, then the integration level and switch speed are improved, but the gate control ability over the channel region is reduced and short-channel effects increase
Solution Approach 1:
The patent transitions from planar MOSFET to FinFET structure, utilizing three-dimensional vertical fins to enhance gate control. The gate wraps around the fin structure from two sides, providing superior electrostatic control over the channel region compared to conventional planar devices, thereby maintaining gate control ability despite channel length scaling.
Solution Approach 2:
The patent implements nested well structures (first well region, second well region, third well region, fourth well region) within the FinFET device. These nested wells are formed at different depths and positions to independently control threshold voltages and optimize device performance, allowing precise electrical characteristic tuning while maintaining scaled dimensions.
2Ease of manufacture
If conventional doping methods are used to form well regions, then the fabrication process is simple, but the dopant distribution is non-uniform affecting threshold voltage and device performance
Solution Approach 1:
The patent divides the doping process into multiple segmented steps, forming different well regions (first well, second well, third well, fourth well) through separate doping operations. Each well is doped independently with specific dopant types and concentrations, enabling precise control over dopant distribution and threshold voltage characteristics while maintaining fabrication feasibility.
Solution Approach 2:
The patent applies local quality by creating spatially varying dopant concentrations at different locations within the device structure. Different well regions receive different dopant treatments (P-type or N-type doping) to locally optimize electrical characteristics, ensuring uniform and precise threshold voltage control across the device while accommodating varying performance requirements in different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the control of the gate over the channel, reduces short-channel effects, and enhances the uniformity and performance of FinFETs, particularly in SRAM devices, by forming super step retrograde wells that increase breakdown voltage and prevent threshold voltage drift.
Implementation Method 1
performing a thermal annealing process to the first doped sidewall spacers and the second doped sidewall spacers to form a third well region in the first fin and a fourth well region in the second fin, respectively
Data Source
AI summary
The present disclosure provides FinFET structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a first well region in first region and a second well region in the second region; forming at least one first fin in the first region and at least one second fin in the second region; forming a first doped layer covering the first fin; forming a second doped layer covering the second fin; forming first doped sidewall spacers on side surfaces of the first fin and second doped sidewall spacers on side surfaces of the second fin by a mask-less etching process; and performing a thermal annealing process to the first doped sidewall spacers and the second doped sidewall spacers to form a third well region in the first fin and a fourth well region in the second fin, respectively.