FinFET Memory Arrays With Segmented Channel Depths
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Solution Overview
Problem
Current finFET devices face challenges in achieving improved architectures and fabrication methods for highly integrated memory and circuitry applications, particularly in optimizing channel region depths and doping levels for enhanced performance.
Innovation Solution
The implementation of a memory array design featuring finFET transistors with subdivided rows of deep-type and shallow-type channel regions, where the deep-type rows have deeper channel regions than the shallow-type rows, and the use of conductive shielding lines for electrical isolation, along with specific doping levels and gate dielectric materials to control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If finFET devices are used in highly integrated memory arrays, then integration density is improved, but fabrication complexity increases
Solution Approach 1:
The memory array is divided into deep-type rows and shallow-type rows with different channel region depths. This segmentation allows different fabrication sequences to be applied to different row types, simplifying the overall fabrication process while maintaining high integration density.
Solution Approach 2:
Different channel region depths are implemented in different rows (deep-type vs shallow-type) to optimize performance for specific applications. This local differentiation allows tailored electrical characteristics in specific regions without complicating the entire device structure.
2Reliability
If channel region depth is increased to improve performance, then electrical performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The channel regions are segmented into deep-type and shallow-type regions with different depths. This segmentation allows each type to be optimized independently, reducing the precision burden on any single fabrication step while achieving overall performance goals.
Solution Approach 2:
Different channel depth parameters are used in different rows to balance performance requirements with manufacturing capabilities. By varying the depth parameter locally rather than uniformly, the patent achieves high electrical performance without requiring extreme precision across the entire array.
3Reliability
If doping levels are optimized to enhance performance, then electrical performance is improved, but device complexity increases
Solution Approach 1:
Different doping levels are applied to deep-type and shallow-type channel regions based on their specific performance requirements. This local quality approach optimizes electrical performance in each region without requiring complex doping profiles across the entire device.
Solution Approach 2:
Doping concentration parameters are varied locally in different row types to achieve optimal electrical performance. By changing doping parameters rather than using a uniform profile, the patent enhances performance without significantly increasing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the performance of finFET devices by allowing for selective activation of current flow and improved electrical isolation, enabling more efficient operation in highly integrated memory arrays.
Implementation Method 1
conductive shielding lines for electrical isolation
Implementation Method 2
gate dielectric materials to control current flow
Data Source
AI summary
Some embodiments include memory arrays having rows of fins. Each fin includes a first pedestal, a second pedestal and a trench between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trench between the first and second pedestals. The rows are subdivided amongst deep-type (D) rows and shallow-type (S) rows, with the deep-type rows having deeper channel regions than the shallow-type rows. Some embodiments include rows of fins in which the channel regions along individual rows are subdivided amongst deep-type (D) channel regions and shallow-type (S) channel regions, with the deep-type channel regions being below the shallow-type channel regions.