FinFET Memory Cell Layout Using Spacer Masks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Standard lithographic techniques are unable to scale down with FinFETs to smaller dimensions, limiting the manufacturing of FinFETs in semiconductor devices like SRAMs, as they face challenges in forming fins and gate electrodes effectively.
Innovation Solution
The use of dummy layers and spacers in the SRAM cell layout allows for the formation of fins and gate electrodes without relying on traditional lithography, enabling smaller dimensions beyond the limitations of photolithographic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If standard lithographic techniques are used to form fins and gate electrodes, then the manufacturing process is simple and well-established, but the minimum achievable dimensions are limited and cannot scale further
Solution Approach 1:
The manufacturing process is divided into multiple sequential steps: forming dummy patterns, depositing spacer material, anisotropically etching spacers, removing dummy patterns, and repeating the process. This segmentation allows each step to be optimized independently, achieving dimensions below lithographic limits while maintaining process control
Solution Approach 2:
Dummy patterns are formed in advance as sacrificial structures to define the positions of fins and gate electrodes. These preliminary structures enable subsequent spacer formation at precise locations, allowing dimensional control that is not achievable through direct lithographic patterning alone
2Length of moving object
If FinFET dimensions are reduced to improve device scaling, then device performance improves, but standard lithographic processes become unable to manufacture the structures
Solution Approach 1:
Spacer structures serve as intermediary elements that transfer the pattern from lithographically-formed dummy patterns to the final fin and gate electrode structures. The spacers act as a bridge, allowing the lithographic process to define locations while the spacer formation process defines the final dimensions, enabling scaling below direct lithographic limits
Solution Approach 2:
The manufacturing approach moves from two-dimensional planar patterning to three-dimensional spacer formation. By depositing conformal spacer layers and using anisotropic etching, the process exploits the vertical dimension to achieve precise lateral dimensioning that is independent of lithographic resolution limits
Data Source
AI summary
A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.