FinFET Memory Cell Protection Layer for Leakage Control
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Solution Overview
Problem
As memory devices shrink, the capacitance between the floating gate and control gate decreases, leading to insufficient drive current for programming, erasing, and reading, and current leakage occurs, especially under high electric fields, reducing reliability and stability.
Innovation Solution
A memory cell design featuring a protection layer on a fin structure to separate charge trapping structures, using a trimming process to miniaturize devices, and employing Fowler-Nordheim tunneling, channel hot electron injection, and band-to-band hot hole tunneling for programming and erasing, with a dielectric protection layer and charge trapping structures on both sidewalls of the fin to prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are shrunk to increase integration level, then storage capacity increases, but drive current becomes insufficient for programming, erasing and reading
Solution Approach 1:
The patent transitions from planar memory structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and capacitance between floating gate and control gate without increasing the planar footprint, thereby maintaining drive current while achieving higher integration density
Solution Approach 2:
The patent implements nested charge trapping structures where first and second charge trapping layers are positioned on opposite sides of the fin structure, with additional charge trapping structures potentially nested within. This nested arrangement maximizes the use of vertical space to increase storage capacity within the same device footprint
2Productivity
If memory cells are shrunk to increase integration level, then storage capacity increases, but current leakage occurs at device corners
Solution Approach 1:
The patent applies different material properties to different regions of the device. Specifically, dielectric materials with appropriate breakdown voltages are used to form isolation structures and charge trapping layers in specific locations, providing localized electrical characteristics that prevent corner leakage while maintaining overall device performance
Solution Approach 2:
The patent introduces intermediate dielectric layers and charge trapping structures between the floating gate and control gate, and between adjacent fins. These intermediary structures act as electrical barriers that prevent direct current leakage paths, especially at critical corner regions where high electric fields concentrate
3Power
If double gate or tri-gate memory cells are used to improve electrical performance, then drive current increases, but manufacturing cost increases and fabrication process becomes complex
Solution Approach 1:
The patent segments the charge trapping function into multiple discrete layers (first and second charge trapping layers) positioned on opposite sides of the fin. This segmentation allows each layer to be formed using separate, well-established deposition processes, avoiding the need for complex multi-step gate formation required in double or tri-gate structures while achieving similar electrical performance
4Power
If tri-gate memory cells are used to improve electrical performance, then drive current increases, but current leakage worsens under high electric field
Solution Approach 1:
The patent extracts the charge trapping function from a continuous gate structure and places it in discrete charge trapping layers on the fin surfaces. This extraction eliminates the corner regions inherent in tri-gate structures where electric field concentration causes leakage, while maintaining the enhanced drive current through increased effective channel area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical performance by preventing current leakage and improving integration level with a simple and cost-effective manufacturing method, allowing for stable and reliable operation of memory cells with increased storage capacity.
Implementation Method 1
a protection layer that separates the charge trapping structure that is disposed between the top of the fin structure and the gate
Implementation Method 2
makes use of Fowler-Nordheim (FN) tunneling to program or erase memory cells
Implementation Method 3
make use of the channel hot electron injection method to program memory cells
Implementation Method 4
make use of the band to -band hot hole tunneling effect to erase memory cells
Data Source
AI summary
A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.