FinFET Memory Deck Alignment via Gating Pitch Modification
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Solution Overview
Problem
Challenges arise in aligning conductive structures such as wordlines and digit lines with CMOS circuitry in integrated memory arrays, affecting the integration density and efficiency of memory architectures.
Innovation Solution
The integration of FinFET arrangements with CMOS regions, where the alignment of conductive lines with circuit arrangements is achieved by modifying the pitch between gating structures, allowing for orthogonal alignment of digit lines with sense-amplifier circuits, thereby enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory array architectures are used, then manufacturing and alignment processes are simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar 2D memory array architecture to a 3D stacked architecture with multiple decks of memory cells vertically stacked above the CMOS region. This dimensional change enables higher integration density by utilizing the vertical space above the base CMOS circuitry, allowing memory decks to be stacked in multiple layers without increasing the lateral footprint of the device.
Solution Approach 2:
The memory array is divided into multiple separate decks, with each deck containing a subset of memory cells. Each deck can be independently formed and aligned, allowing the complex 3D structure to be built incrementally through multiple fabrication stages. This segmentation enables precise alignment of conductive structures within each deck while maintaining overall system integration.
2Manufacturing precision
If pitch between gating structures is reduced to increase density, then integration density improves, but alignment precision becomes more difficult to achieve
Solution Approach 1:
By stacking multiple memory decks vertically, the patent achieves higher integration density in the vertical dimension rather than compressing the lateral pitch between gating structures. This allows each deck to maintain adequate pitch dimensions for precise alignment while still achieving high overall density through the stacked configuration of multiple decks above the CMOS region.
3Quantity of substance
If more memory cells are packed into smaller space, then integration density increases, but alignment of conductive structures with CMOS circuitry becomes more challenging
Solution Approach 1:
The patent divides the high-density memory array into multiple separate decks, where each deck contains a manageable subset of memory cells. This segmentation allows each deck to be independently aligned with the CMOS circuitry below, reducing the overall alignment complexity that would result from attempting to align a single large-scale high-density array. The modular deck structure enables precise alignment to be achieved through multiple staged alignment processes.
Solution Approach 2:
The patent forms each memory deck in a staged fabrication process, where preliminary alignment and registration structures are established before forming subsequent decks. This preliminary action ensures that each deck is pre-aligned with the CMOS circuitry and with previous decks, maintaining manufacturing precision throughout the multi-deck stacking process while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise alignment of conductive structures with CMOS devices, improving integration density and efficiency in memory architectures, allowing for more compact and high-density memory array configurations.
Implementation Method 1
The capacitor may electrostatically store energy as an electric field within capacitor dielectric between two capacitor electrodes
Data Source
AI summary
Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.