FinFET Memory Device Gate Segmentation for Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reducing the size of memory cell arrays while maintaining effective capacitive coupling and operational efficiency, as thinning the BOX layer increases transistor capacity and costs, and adopting FinFETs results in larger memory cell arrays.
Innovation Solution
The semiconductor memory device employs Fin semiconductors with source and drain layers, floating bodies for data storage, and divided gate electrodes to enable efficient data storage and retrieval, allowing for orthogonal arrangement of word and bit lines, which reduces the size of the memory device by eliminating unnecessary spaces between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the BOX layer is made thin to increase capacitive coupling, then the signal difference is improved, but the transistor capacity increases and operation is decelerated
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) positioned on opposite sides of the Fin semiconductor. This segmentation allows independent control of the floating body, enabling strong capacitive coupling for data storage while maintaining proper transistor operation speed through balanced voltage control.
Solution Approach 2:
The patent applies different voltages to the first and second gate electrodes to create localized electric field control. By optimizing the voltage distribution across the Fin semiconductor, the patent achieves strong capacitive coupling in the storage region while preventing excessive capacity effects that would slow down transistor operation.
2Measurement precision
If the BOX layer is made thin to increase capacitive coupling, then the signal difference is improved, but the manufacturing cost increases
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) positioned on opposite sides of the Fin semiconductor. This segmentation allows independent control of the floating body, enabling strong capacitive coupling for data storage while maintaining proper transistor operation speed through balanced voltage control.
Solution Approach 2:
The patent applies different voltages to the first and second gate electrodes to create localized electric field control. By optimizing the voltage distribution across the Fin semiconductor, the patent achieves strong capacitive coupling in the storage region while preventing excessive capacity effects that would slow down transistor operation.
3Reliability
If FinFETs are adopted as FBCs, then the capacitive coupling is maintained, but the memory cell array size increases
Solution Approach 1:
The patent transitions from planar gate configuration to a three-dimensional FinFET structure with gates wrapping around the Fin semiconductor from opposite sides. This dimensional change enables effective capacitive coupling through vertical field control while maintaining a compact footprint by utilizing the third dimension (depth of Fin) rather than expanding the planar area.
Solution Approach 2:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) positioned on opposite sides of the Fin semiconductor. This segmentation allows independent control of the floating body, enabling strong capacitive coupling for data storage while maintaining proper transistor operation speed through balanced voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a downsized semiconductor memory device with improved operational efficiency and reduced costs, as it enables sharing of gate electrodes between adjacent memory cells, thereby minimizing the device's footprint without compromising performance.
Implementation Method 1
capacitive coupling between the body and the substrate (fixed potential) is set strong so as to increase a signal difference
Data Source
AI summary
This disclosure concerns a semiconductor memory device including Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.