FinFET Memory Gate Separation Trench Insulator
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Solution Overview
Problem
One-time programmable (OTP) non-volatile memory devices, such as those using fuses or antifuses, are irreversible and cannot be modified without additional devices, limiting their functionality and flexibility.
Innovation Solution
A semiconductor device with fin-type active patterns and gate electrodes is designed, featuring a trench with an embedded insulator in the gate-separating region, allowing for improved sensing windows and programmable transistors that can form resistive shorts, enabling efficient manufacturing and enhanced reading operation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional OTP memory device is programmed using fuse or antifuse, then the programming is irreversible and the device cannot be modified without additional devices, but this limits the functionality and flexibility of the memory device
Solution Approach 1:
The active pattern is divided into multiple fins (first fin active pattern and second fin active pattern) with separate gate electrodes (first gate electrode and second gate electrode) controlling different channel regions. This segmentation allows independent control of programming and reading operations, enabling the device to function as both OTP and reconfigurable memory without requiring additional devices.
Solution Approach 2:
The semiconductor device is designed to perform multiple functions: it can operate as a conventional OTP memory for irreversible storage, as a reconfigurable memory that can be programmed and erased multiple times, and as a device with enhanced reading operation characteristics. This multi-functionality is achieved through the dual-gate finFET structure that enables different operational modes.
2Measurement precision
If the second gate electrode is extended in a direction different from the first direction to cross the first gate-separating region, then the sensing window is improved, but the device structure becomes more complex
Solution Approach 1:
The second gate electrode is extended in a direction different from the first direction (crossing the gate-separating region), utilizing a different spatial dimension to achieve improved sensing window characteristics. This dimensional change allows the gate electrode to control multiple channel regions more effectively, enhancing the reading operation without proportionally increasing overall device complexity.
3Reliability
If fin-type active patterns with gate electrodes are used, then the ratio of ON-current to OFF-current is increased, but the manufacturing process becomes more complex
Solution Approach 1:
The first and second fin active patterns are formed in close proximity and share common structural elements (substrate, insulator layers, contact portions), merging multiple functions into a unified structure. This integration approach achieves high current ratios while reducing the overall manufacturing complexity compared to implementing separate devices for different functions.
Data Source
AI summary
A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first and second fin type active patterns include a first channel region disposed between a first impurity region and a second impurity region. The second gate electrode pattern crosses a first gate-separating region included in the second fin type active region. The first gate-separating region includes a trench and an embedded insulator filling at least a portion of the trench.