FinFET Memory Structure Integrating DRAM and SONOS
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Solution Overview
Problem
The miniaturization of electronic devices is hindered by the need for separate volatile and non-volatile memory devices, which increases size and decreases data transfer speed due to the separate construction and operation of these memory types.
Innovation Solution
A high aspect ratio FinFET structure with both volatile and non-volatile memory portions is developed, allowing data transfer between these portions, eliminating the need for additional non-volatile memory devices and enhancing data transfer speed by integrating SONOS and DRAM cells within a single memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate volatile and non-volatile memory devices are used, then data storage reliability is improved, but device size increases and data transfer speed decreases
Solution Approach 1:
The patent combines volatile DRAM and non-volatile SONOS memory cells into a single integrated memory structure. Each memory cell contains both a DRAM portion (with capacitor and transistor) and a SONOS portion (with charge trap layer), allowing data to be stored simultaneously in volatile and non-volatile states within the same physical cell, thereby eliminating the need for separate memory devices while maintaining data reliability.
Solution Approach 2:
The integrated memory cell performs multiple functions: it can operate as volatile DRAM for fast data access, as non-volatile SONOS for data retention without power, and transfer data between the two states. This multi-functionality allows a single memory device to replace what would traditionally require separate volatile and non-volatile memory devices, reducing overall device size.
2Reliability
If separate volatile and non-volatile memory devices are used, then data storage reliability is improved, but data transfer speed decreases
Solution Approach 1:
By merging DRAM and SONOS functionality into a single memory cell, the patent enables direct data transfer between volatile and non-volatile storage portions without requiring external data movement between separate devices. The shared transistor and closely coupled cell structure allow rapid data transfer between the capacitor and charge trap layer, significantly improving data transfer speed while maintaining the reliability benefits of non-volatile storage.
3Adaptability or versatility
If high aspect ratio FinFET structure is used, then integration of volatile and non-volatile portions is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a high aspect ratio FinFET structure where the transistor channel extends vertically from the substrate. This three-dimensional configuration allows the gate to wrap around the fin structure, providing superior gate control and enabling the integration of both DRAM and SONOS portions within a compact footprint. The vertical dimension accommodates the multiple layers (oxide layers, nitride layers, charge trap layers) required for both memory types, achieving high integration while managing manufacturing complexity through standardized FinFET fabrication processes.
Data Source
AI summary
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.