FinFET Merged Source/Drain Doping Structure for Lower Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, there is a need to reduce device electrical resistance to improve performance, which existing technologies have not adequately addressed, particularly in the context of fin field effect transistors (Fin FETs) with metal gate structures.
Innovation Solution
The solution involves forming epitaxial source/drain structures with multiple layers of varying dopant concentrations and geometries to reduce resistance, including a first layer as a protective layer, a second layer merging with adjacent structures, and a third layer extending into recesses to increase dopant concentration and surface area for better contact, followed by a metal-semiconductor compound layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are reduced to increase device density, then device density is improved, but electrical resistance increases
Solution Approach 1:
The patent transitions from planar 2D source/drain structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel width and surface area for carrier transport without increasing the lateral footprint, thereby maintaining high device density while improving electrical characteristics through enhanced surface area for current flow
Solution Approach 2:
The patent employs a composite material structure with a high-k dielectric material (such as hafnium oxide) combined with a metal gate material. The high-k material provides superior gate control with lower leakage compared to traditional silicon dioxide, enabling better electrical performance at scaled dimensions while maintaining device density
2Reliability
If high-k dielectric material is used in gate structure, then gate control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the high-k dielectric material layer and metal gate structure before source/drain epitaxial growth and doping. This sequence allows the gate structure to be established with proper dimensions and materials prior to subsequent processing steps, simplifying the overall manufacturing by pre-defining critical dimensions and avoiding rework in later stages
Solution Approach 2:
The gate structure is segmented into distinct functional layers: a high-k dielectric material layer providing electrical isolation and capacitance, and a metal gate layer providing work function control and signal transmission. This segmentation allows each layer to be optimized independently for its specific function while simplifying the manufacturing process through modular deposition and processing steps
3Reliability
If epitaxial growth method is used for source and drain formation, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by implementing selective doping strategies where different dopant concentrations and types are introduced into specific regions of the source/drain structures. The epitaxial growth process creates regions with varying dopant profiles tailored to local electrical requirements, such as heavily doped contact regions for low resistance and lightly doped channel regions for proper carrier modulation, thereby optimizing device performance while managing manufacturing precision through localized control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced electrical resistance, improved device performance with increased DC Ideff and reduced channel resistance, and enhanced surface area for metal contacts, leading to faster device speed and lower parasitic capacitance.
Implementation Method 1
sources and drains are formed by using an epitaxial growth method
Data Source
AI summary
Semiconductor device manufacturing includes forming fins over substrate extending in first direction. Gate is formed over fin's first portion, gate extends in second direction crossing first. Fin mask layer formed on fin sidewalls. Fin second portions are recessed, wherein second portions are located on opposing gate sides. Epitaxial source/drains are formed over recessed fins. Epitaxial source/drain structures include first layer having first dopant concentration, second layer having second dopant concentration, and third layer having third dopant concentration. Third concentration is greater than second concentration, second concentration is greater than first concentration. At least adjacent third layers source/drains merge thereby form merged source/drains, and height in third direction substantially perpendicular to first and second directions from upper surface of adjacent fins to merged source/drain lower surface uppermost point is greater than thickness of merged source/drain in third direction from lower surface uppermost point of source/drain to source/drain top surface.