FinFET Merged Source-Drain Epitaxy for Low External Resistance
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Solution Overview
Problem
Conventional planar FET scaling has reached fundamental limits, necessitating unconventional geometries for continued semiconductor device performance improvements, particularly in fin field effect transistors (FinFETs), where merging epitaxial semiconductor material for source and drain regions poses challenges due to high external resistance and parasitic capacitance.
Innovation Solution
A method involving the growth of epitaxial semiconductor material with specific orientations and geometries on fin structures, including diamond-shaped and rectangular geometries, to reduce external resistance and parasitic capacitance by merging epitaxial material between adjacent fin structures, utilizing etching processes to expose appropriate surfaces for uniform growth and blocking materials to manage growth termination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar FET scaling is continued, then device density improves, but fundamental performance limits are reached
Solution Approach 1:
The patent transitions from planar 2D FET geometry to 3D FinFET geometry by introducing vertical fins that extend from the substrate. This dimensional change increases the effective channel area and device density while maintaining controllable gate electrostatics, thereby improving productivity without sacrificing reliability.
2Reliability
If epitaxial material is merged between adjacent fin structures, then external resistance and parasitic capacitance are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges epitaxial semiconductor material between adjacent fin structures to form shared source and drain regions. This merging reduces the number of discrete contacts required, thereby reducing external resistance and parasitic capacitance. The process integrates multiple functions into a single epitaxial growth step, managing complexity through process integration.
Solution Approach 2:
The patent performs preliminary epitaxial growth of semiconductor material on the fin structures before final device assembly. This preliminary action establishes the merged source and drain regions in advance, simplifying subsequent processing steps and reducing the complexity of later manufacturing operations.
3Productivity
If fin structures are scaled below 30 nm pitches, then device density improves, but control over epitaxial growth and merging becomes more difficult
Solution Approach 1:
The patent applies local quality by providing different crystallographic orientations for different regions of the fin structures. Specific surface orientations are selected to promote uniform epitaxial growth and proper merging behavior at sub-30 nm pitches, thereby maintaining manufacturing precision while achieving high device density.
Solution Approach 2:
The patent utilizes parameter changes by controlling the crystallographic orientation and geometry of the epitaxial growth. By adjusting growth parameters and surface orientations, the process achieves uniform material deposition and merging even at reduced pitch dimensions, maintaining manufacturing precision while improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in FinFETs with reduced external resistance and parasitic capacitance, enabling effective scaling of fin structures below 30 nm pitches by optimizing the geometry and orientation of epitaxial growth, thereby enhancing device performance.
Implementation Method 1
A first epitaxial semiconductor material having a diamond geometry is grown on the diamond shaped epitaxial growth surface
Data Source
AI summary
A method of forming a semiconductor device that includes providing a plurality of fin structures, wherein a surface of the fin structures has a first orientation for a diamond shaped epitaxial growth deposition surface. A first epitaxial semiconductor material having a diamond geometry is grown on the diamond shaped epitaxial growth surface. A blocking material is formed protecting a lower portion of the first epitaxial semiconductor material. An upper portion of the first epitaxial semiconductor material is removed to expose a second orientation surface of the first epitaxial semiconductor material for merged epitaxial semiconductor growth. A second epitaxial semiconductor material is epitaxially formed on the first epitaxial semiconductor material. The second epitaxial semiconductor material has a substantially planar upper surface and extends into direct contact with at least two adjacent fin structures.