FinFET and Mesa Transistor Integration for Mixed-Voltage Circuits
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Solution Overview
Problem
FinFETs are not suitable for use as medium-voltage and high-voltage transistors in circuit designs, necessitating the integration of multiple transistor types on a single semiconductor substrate.
Innovation Solution
The integration of core, low-voltage, medium-voltage, and high-voltage transistors on a single semiconductor substrate using semiconductor fins and mesa structures, with dielectric or polysilicon plugs in the gates, and shared formation processes to reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FinFETs are used for core and low-voltage transistors, then speed and performance are improved, but they cannot be used for medium-voltage and high-voltage transistors
Solution Approach 1:
The semiconductor substrate is divided into multiple regions with different transistor structures: FinFETs for core/LV transistors and planar transistors for MV/HV transistors. This segmentation allows each region to be optimized for its specific voltage requirements while maintaining overall system performance.
Solution Approach 2:
Different transistor structures are implemented in different locations on the substrate based on local voltage requirements. FinFETs with vertical channels provide high speed for low-voltage operations, while planar transistors with horizontal channels provide voltage breakdown tolerance for medium and high voltage operations.
2Adaptability or versatility
If multiple types of transistors are integrated on a single substrate, then versatility is improved, but manufacturing complexity increases
Solution Approach 1:
A unified manufacturing process is developed that can produce multiple transistor types (FinFET and planar) using the same equipment and process steps. The process uses common materials and techniques, with only minor process variations needed to switch between transistor types, thereby reducing overall manufacturing complexity.
Solution Approach 2:
The substrate is prepared in advance with pre-formed regions that will become different transistor types. Etch masks and other structural elements are pre-configured to define where FinFETs and planar transistors will be formed, simplifying the subsequent manufacturing steps.
3Reliability
If different transistor structures are used for different voltage requirements, then functional performance is improved, but manufacturing cost increases
Solution Approach 1:
The manufacturing process is designed to produce multiple transistor types using the same equipment and process flow. By using common process steps, materials, and equipment for both FinFET and planar transistor fabrication, the incremental cost of producing multiple transistor types is minimized.
Data Source
AI summary
A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.