FinFET Metal Gate Cutting With Etch Protection Layers
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Solution Overview
Problem
Conventional metal gate cutting techniques for FinFETs struggle to remove metal residue at smaller technology nodes, leading to potential isolation issues and changes in critical dimensions due to horizontal etching, which constrains the miniaturization of integrated circuits.
Innovation Solution
The method involves creating a cut window in an overlaying patterning layer to expose metal gate structures and inter-layer dielectric layers, using anisotropic etching with an etch protection layer to remove the exposed materials in thickness increments, preventing horizontal expansion of the cut window and ensuring residue-free cutting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal gate cutting techniques are used, then the cutting process is simple, but metal residue remains and critical dimensions change due to horizontal etching
Solution Approach 1:
The etching process is divided into multiple sequential etching cycles, each removing a portion of the metal gate structure. Between cycles, an etch protection layer is deposited to protect already-etched regions. This segmentation allows precise control over etching depth and prevents horizontal expansion, achieving complete metal removal without residue while maintaining critical dimensions.
Solution Approach 2:
An etch protection layer is deposited on the substrate before the etching process begins. This preliminary action protects the substrate and previously etched regions from unwanted etching, enabling precise control over the etching depth and preventing horizontal expansion of the cut window throughout subsequent etching cycles.
2Manufacturing precision
If etching is performed to remove metal gate portions, then metal residue is removed, but horizontal expansion of cut window occurs changing critical dimensions
Solution Approach 1:
An etch protection layer is deposited on the substrate before the etching process begins. This preliminary action protects the substrate and previously etched regions from unwanted etching, enabling precise control over the etching depth and preventing horizontal expansion of the cut window throughout subsequent etching cycles.
Solution Approach 2:
The etching process is divided into multiple sequential etching cycles, each removing a portion of the metal gate structure. Between cycles, an etch protection layer is deposited to protect already-etched regions. This segmentation allows precise control over etching depth and prevents horizontal expansion, achieving complete metal removal without residue while maintaining critical dimensions.
3Manufacturing precision
If multiple etching cycles are used to remove metal residue, then cutting precision improves, but processing time increases
Solution Approach 1:
The etching process is divided into multiple sequential etching cycles, each removing a portion of the metal gate structure. Between cycles, an etch protection layer is deposited to protect already-etched regions. This segmentation allows precise control over etching depth and prevents horizontal expansion, achieving complete metal removal without residue while maintaining critical dimensions.
Solution Approach 2:
The etching cycles are performed in sequence with etch protection layer deposition between them, maintaining continuous progress toward complete metal removal. Each cycle builds upon the previous one, systematically eliminating metal residue while the etch protection layer prevents back-etching, ensuring efficient use of processing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables residue-free cutting of metal gate structures, maintaining the critical dimensions and preventing isolation issues, thus enhancing the operation and performance of FinFET devices.
Implementation Method 1
using anisotropic etching with an etch protection layer to remove the exposed materials in thickness increments
Data Source
AI summary
Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.