FinFET Metal Gate Extending Into Isolation Layer
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating high-performance Fin FET devices due to difficulties in controlling electrical properties and achieving uniformity in metal gate structures, particularly in forming gate structures with high aspect ratios and extending portions that enhance effective area without compromising yield and increasing the risk of leakage or bridging.
Innovation Solution
A 'gate-last' process is employed to form a metal gate structure with an extending portion that extends into the isolation insulating layer, adjusting electrical properties and enlarging the effective area, while maintaining uniformity and reducing manufacturing complexity by avoiding additional masking or alignment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate structures with high aspect ratios and extending portions are formed to enhance effective area, then device performance is improved, but manufacturing uniformity deteriorates and yield decreases
Solution Approach 1:
The gate structure is segmented into multiple functional portions: a first gate portion formed over the fin structure and a second gate portion formed over the isolation insulating layer. This segmentation allows each portion to be optimized independently for its specific function, improving overall manufacturing uniformity while maintaining enhanced effective area.
Solution Approach 2:
The gate structure extends in the vertical dimension by forming a second gate portion over the isolation insulating layer, creating an extending portion that increases effective area without compromising planar manufacturing uniformity. This dimensional approach separates the performance enhancement function from the manufacturing precision requirement.
2Reliability
If gate structures with larger heights are formed to control electrical properties, then electrical control is improved, but leakage and bridging risks increase
Solution Approach 1:
Different portions of the gate structure have different heights and configurations optimized for their local functions. The first gate portion provides electrical control over the fin structure, while the second gate portion extending over the isolation insulating layer provides additional control without creating leakage paths, as each portion's dimensions are locally optimized.
Solution Approach 2:
The isolation insulating layer serves as an intermediary that supports the second gate portion while electrically isolating it from underlying structures. This intermediary enables the gate structure to achieve larger effective area and improved electrical control without direct contact that would cause leakage or bridging.
3Manufacturing precision
If additional masking or alignment processes are used to form complex gate structures, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The formation of the first and second gate portions is merged into a single continuous gate structure formed by one deposition process. This merging eliminates the need for separate masking and alignment steps between the two gate portions, reducing process complexity while maintaining the precision benefits of the multiportion design.
Solution Approach 2:
The single gate structure serves multiple functions: the first gate portion provides electrical control over the fin structure, while the second gate portion extending over the isolation insulating layer provides additional electrical control and defines device boundaries. This multi-functionality is achieved without additional process steps.
Data Source
AI summary
A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.