FinFET Metal Gate Profiles for Threshold Voltage Tuning
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving proper threshold voltages (Vt) for boosting performance while reducing power consumption, particularly in three-dimensional designs like FinFETs and gate-all-around FETs, where there is limited room for tuning Vt using different work function metals.
Innovation Solution
A method is developed to control the height of the metal gate profile by recessing the metal gate structure and forming a cap insulating layer to isolate it from adjacent conductive contacts, allowing for the fabrication of FinFETs with different threshold voltages through precise metal gate design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different work function metals are used to tune threshold voltages, then threshold voltage tuning capability is improved, but device complexity and manufacturing difficulty increase due to limited room for tuning in three-dimensional designs
Solution Approach 1:
The patent changes the physical parameters of the gate electrode structure by controlling its height relative to the channel region and forming insulating layers at specific positions. This allows threshold voltage tuning through geometric parameter adjustment rather than changing material composition, thereby maintaining adaptability while reducing device complexity
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the gate electrode and the channel region. This intermediary structure enables precise control of the electric field and threshold voltage without requiring complex metal stack configurations, simplifying the overall device structure while maintaining tuning capability
2Manufacturing precision
If metal gate structure is recessed and isolated with cap insulating layer, then threshold voltage control precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the insulating layer and adjusting the gate electrode height before final device assembly. This preliminary structuring enables precise threshold voltage control to be established early in the manufacturing process, simplifying subsequent steps while maintaining high precision
Solution Approach 2:
The patent applies local quality by forming insulating layers at specific locations (between the gate electrode and channel region) rather than uniformly throughout the structure. This localized approach achieves precise threshold voltage control only where needed, optimizing manufacturing precision without unnecessarily increasing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FinFETs with tailored threshold voltages, enhancing performance and reducing power consumption by optimizing the metal gate profile and isolation, thereby addressing the limitations of existing Vt tuning methods.
Implementation Method 1
an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer
Data Source
AI summary
In a method of manufacturing a semiconductor device, a gate space is formed by removing a sacrificial gate electrode formed over a channel region, a first gate dielectric layer is formed over the channel region in the gate space, a second gate dielectric layer is formed over the first gate dielectric layer, one or more conductive layers is formed on the second gate dielectric layer, the second gate dielectric layer and the one or more conductive layers are recessed, an annealing operation is performed to diffuse an element of the second gate dielectric layer into the first gate dielectric layer, and one or more metal layers are formed in the gate space.