Fin-FET Metal Silicide Formation via Double Patterning
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Solution Overview
Problem
As semiconductor devices shrink in size, the fabrication of Fin-FETs becomes more difficult due to challenges in forming accurate metal silicide layers, leading to poor electrical performance due to issues like overlay alignment, line end, and corner rounding, which affect the morphology and stability of the metal silicide layers.
Innovation Solution
A double-patterning method is used with two masks of different materials to form discrete patterned layers that cover the source, drain, and isolation areas, allowing for precise etching to create contact vias and metal silicide layers, avoiding alignment issues and improving morphology accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional single-patterning method is used to form metal silicide layers, then the fabrication process is simpler, but the position and morphology accuracy deteriorates due to overlay alignment issues, line end effects, and corner rounding
Solution Approach 1:
The patent divides the patterning process into two separate steps: first forming a mandrel pattern, then using it to create the final metal silicide layer pattern. This segmentation allows each step to be optimized independently, avoiding the overlay alignment issues that would occur in a single-step process while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element that facilitates the formation of the metal silicide layer. The mandrel serves as a temporary pattern that guides the deposition and etching processes, enabling high precision without requiring direct alignment between multiple lithographic steps.
2Productivity
If device size is reduced to increase component density, then the integration degree improves, but the ability to control channel current deteriorates due to short channel effect and leakage current
Solution Approach 1:
The patent transitions from planar transistor geometry to Fin-FET structure, adding a vertical dimension to the channel. This dimensional change increases the effective channel width without increasing the planar footprint, thereby maintaining high component density while improving gate control over the channel current and reducing short channel effects.
3Reliability
If Fin-FET structure is used to overcome short channel effect, then channel current control improves, but the fabrication difficulty increases due to challenges in forming accurate metal silicide layers at smaller process nodes
Solution Approach 1:
The patent performs preliminary patterning to create the mandrel structure before forming the metal silicide layer. This preliminary action establishes a precise template that guides subsequent deposition and etching steps, making the overall fabrication process more controllable and less complex despite the advanced Fin-FET structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the position and morphology accuracy of contact vias and metal silicide layers, improving the electrical properties and performance of semiconductor devices by reducing overlay and corner rounding issues, thus improving process flexibility and device reliability.
Implementation Method 1
forming a patterned second mask layer by etching the second mask layer using the first patterned layers as an etch mask until a portion of the first mask layer is exposed
Implementation Method 2
The second mask layer and the first mask layer are made of different materials
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.