FinFET-Compatible Metal-Insulator-Metal Capacitor Integration
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Solution Overview
Problem
The integration of compact high capacitance capacitors with finFET structures in semiconductor chips is challenging due to altered processing steps and the inability to form conventional planar capacitors on substrates with finFETs, requiring innovative methods to minimize additional processing steps and maintain high integration while optimizing capacitance.
Innovation Solution
A metal-insulator-metal capacitor (MIMCAP) structure is formed by depositing a lower conductive layer on semiconductor fins, followed by a node dielectric and an upper conductive plate, with a gate dielectric on the fin sidewalls, allowing for concurrent fin formation with field effect transistors and optional buried insulator recessing to increase capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar capacitor formation methods are used on finFET substrates, then the capacitor structure is simple and processing steps are minimal, but the capacitor cannot be formed because the upper portion of the semiconductor substrate cannot serve as a lower plate
Solution Approach 1:
The capacitor structure is segmented into distinct lower and upper conductive plates separated by a dielectric layer. The lower conductive plate is formed independently on the insulator material layer rather than using the semiconductor substrate, allowing the capacitor to be formed on finFET substrates where conventional planar methods fail.
Solution Approach 2:
The capacitor structure transitions from a planar two-dimensional configuration to a three-dimensional vertical stack. The lower conductive plate, dielectric layer, and upper conductive plate are stacked vertically, with the lower plate contacting the insulator material layer and the upper plate positioned above, enabling capacitor formation on finFET substrates by utilizing the vertical dimension rather than relying on the substrate surface.
2Area of moving object
If compact high capacitance capacitors are designed to reduce circuit area, then integration density increases, but the number and complexity of additional processing steps increases
Solution Approach 1:
The capacitor formation process is merged with the existing finFET fabrication process. The lower conductive plate is formed concurrently with other semiconductor fins for field effect transistors, and the same dielectric layer is patterned to form both the node dielectric for the capacitor and the gate dielectric for the finFETs, reducing the number of additional processing steps.
Solution Approach 2:
The insulator material layer serves multiple functions: it acts as the lower electrode substrate for the capacitor, provides electrical isolation for the finFET structures, and enables the formation of both capacitor and transistor components on the same substrate. The dielectric layer also serves dual purposes as both node dielectric and gate dielectric.
3Reliability
If additional processing steps are added to form capacitors on finFET substrates, then capacitor functionality is achieved, but total processing time and cost increase
Solution Approach 1:
The lower conductive plate is formed in advance during the finFET fabrication process, concurrently with the formation of other semiconductor fins. This preliminary action ensures that the lower plate is already in place when capacitor formation is initiated, eliminating the need for separate lower plate formation steps and reducing total processing time.
Solution Approach 2:
The existing finFET fabrication process serves the dual purpose of creating both the transistor structures and the capacitor components. The same processing steps that form the finFETs also form the capacitor structures, allowing the process to serve itself rather than requiring entirely separate capacitor fabrication steps.
Data Source
AI summary
At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.