Mismatched Gate End Widths in FinFET Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in reliably producing sub-half micron and smaller features for next-generation VLSI and ULSI devices, particularly in forming gate structures with smaller dimensions due to photolithography limitations, which affect the electrical performance of FinFET devices.
Innovation Solution
The solution involves forming semiconductor device structures with mismatched gate end widths, where a photomask reticle with designed patterns is used to create gate structures with reduced gate end widths, enhancing the thickness of the work function metal layer to improve electrical performance, and utilizing a process that includes photolithography and etching to achieve these dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If photolithography is used to form gate structures with smaller dimensions, then gate dimensions can be reduced to increase device density, but manufacturing precision deteriorates due to photolithography limitations
Solution Approach 1:
The gate structure formation is divided into multiple steps: first forming a mandrel structure, then depositing a first material layer, followed by a second material layer with different etch selectivity. This segmentation allows each layer to be formed with precise control, overcoming the limitations of single-step photolithography and enabling sub-half micron gate dimensions with high manufacturing precision.
Solution Approach 2:
A mandrel structure is introduced as an intermediary element to define the gate pattern. The mandrel serves as a template that guides the subsequent deposition and etching processes, allowing precise gate dimension control that is not achievable through photolithography alone. This intermediary structure enables the formation of sub-half micron gates with high precision.
2Productivity
If gate structures with smaller dimensions are formed, then device density increases, but electrical performance deteriorates due to increased short channel effects
Solution Approach 1:
The gate structure employs different materials with different etch selectivities at different locations: a first material layer and a second material layer. This local quality differentiation allows precise control of the gate end width, enabling smaller gate dimensions for higher device density while maintaining adequate gate control to reduce short channel effects and preserve electrical performance.
Solution Approach 2:
The invention changes the etch selectivity parameter by using materials with different etch rates. The first material layer has different etch selectivity compared to the second material layer, allowing selective removal of material to precisely control gate dimensions. This parameter change enables formation of sub-half micron gates with controlled gate end widths, achieving high device density while maintaining electrical performance through reduced short channel effects.
3Reliability
If work function metal layer thickness is increased, then electrical performance improves, but gate structure complexity increases
Solution Approach 1:
The gate structure uses layers with uniform material composition and consistent etch selectivity characteristics. The first material layer and second material layer each have homogeneous properties that simplify the deposition and etching processes. This homogeneity allows increased work function metal layer thickness for improved electrical performance without proportionally increasing structural complexity, as the uniform layers can be processed using standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for enhanced electrical performance by increasing the thickness of the work function metal layer, reducing short channel effects, and improving current flow in FinFET devices, while maintaining control over gate dimensions to prevent overgrowth and short circuits.
Implementation Method 1
utilizing a process that includes photolithography and etching to achieve these dimensions
Implementation Method 2
utilizing a process that includes photolithography and etching to achieve these dimensions
Data Source
AI summary
Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width