FinFET Circuits with Mixed Design Rules for Higher EM Current
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Solution Overview
Problem
Existing semiconductor structures face limitations in achieving higher operating speeds and smaller device sizes due to the use of analog circuit design rules and analog fin boundaries, which restrict performance improvements as manufacturing processes are scaled down.
Innovation Solution
Design and manufacture circuits using a combination of analog and digital circuit design rules and fin boundaries, where analog circuits use analog fin boundaries and digital circuits use digital fin boundaries, allowing for improved device parameters such as trans-conductance (GM), unit gain frequency (UGF), and electromigration (EM) by employing different via and metal line configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog circuit design rules and analog fin boundaries are used, then device size can be reduced through scaling, but operating speed and performance parameters (GM, UGF, EM) cannot be sufficiently improved
Solution Approach 1:
The patent divides the circuit into analog portions and digital portions, each governed by different design rules and fin boundaries. Analog circuits use analog design rules with analog fin boundaries, while digital circuits use digital design rules with digital fin boundaries, allowing each segment to be optimized for its specific function without compromise
Solution Approach 2:
Different regions of the circuit are assigned different design rule qualities: analog regions receive analog design rules that optimize for performance parameters (GM, UGF, EM), while digital regions receive digital design rules optimized for density and scaling. This local differentiation resolves the contradiction by allowing high performance where needed without sacrificing overall manufacturability
2Reliability
If larger contact poly pitch, wider metal over diffusion, larger vias, wider metal lines, and larger spaces are used, then trans-conductance, unit gain frequency, and electromigration current are improved, but device size increases
Solution Approach 1:
The patent segments the circuit into analog and digital portions, confining larger via, wider metal line, and increased spacing requirements to only the analog portion where performance and reliability are critical. The digital portion maintains compact dimensions, thus achieving improved EM current and GM in analog circuits without proportionally increasing overall device size
Solution Approach 2:
Different spatial qualities are applied to different circuit regions: analog regions implement larger vias, wider metal lines, and increased spacing to improve EM current and GM, while digital regions maintain compact geometries. This localized application of quality enhancements resolves the contradiction between reliability improvement and device size control
3Area of stationary object
If digital fin boundaries are used without keep-out zones, then space efficiency and density are improved, but direct placement of digital logic cells may interfere with analog circuit performance
Solution Approach 1:
The patent clearly segments analog and digital circuits with defined boundaries. Digital logic cells are placed using digital fin boundaries without keep-out zones, maximizing space efficiency in digital regions. Analog circuits are isolated in dedicated regions with analog fin boundaries, preventing interference from digital placements while maintaining overall high density through efficient space utilization
Data Source
AI summary
An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.