FinFET Cell Row Layout With Mixed Heights for Stable Drive Current
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Solution Overview
Problem
In semiconductor manufacturing, manufacturing variations cause significant shifts in parasitic resistance, leading to variations in operating current through transistors, affecting performance indexes like timing, noise, and reliability.
Innovation Solution
The implementation of a semiconductor device with interlaced cell rows of different heights, where cell rows with higher row heights (RH1) have more fin-shaped structures for higher performance and those with lower row heights (RH2) have fewer structures for lower power consumption, along with specific power rail configurations to stabilize power signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are downscaled to increase drive current, then drive current increases, but manufacturing variations cause significant shifts in parasitic resistance affecting performance
Solution Approach 1:
The patent applies local quality by creating different cell row heights (RH1 and RH2) with different numbers of fin-shaped structures. High-performance cell rows have greater row height and more fins to provide higher drive current, while low-power cell rows have smaller row height and fewer fins to reduce power consumption. This local differentiation allows each region to be optimized for its specific performance requirement, resolving the contradiction between achieving high drive current and maintaining performance stability against manufacturing variations.
2Power
If cell rows have more fin-shaped structures for higher performance, then drive current and performance increase, but power consumption increases
Solution Approach 1:
The patent segments the cell rows into two distinct groups: high-performance cell rows with greater row height (RH1) and more fin-shaped structures, and low-power cell rows with smaller row height (RH2) and fewer fin-shaped structures. This segmentation allows the semiconductor device to have different performance characteristics in different regions, enabling high performance where needed while reducing power consumption in other areas, thus resolving the contradiction between performance and power consumption.
3Manufacturing precision
If manufacturing variations occur, then parasitic resistance shifts significantly, but performance indexes like timing and reliability are affected
Solution Approach 1:
The patent changes the geometric parameters of the cell rows by creating two distinct row heights (RH1 and RH2) with different numbers of fin-shaped structures. This parameter differentiation allows for optimized electrical characteristics in each cell row type. By carefully designing the geometric parameters, the patent compensates for manufacturing variations in parasitic resistance, as the different configurations provide different electrical characteristics that can maintain performance indexes like timing and reliability despite variations in manufacturing precision.
Data Source
AI summary
A semiconductor device includes first and second cell rows, first to fourth fin shaped structures. The first cell row has a first row height. The second cell row is adjacent with the first cell row, and having a second row height. The first fin shaped structure extends across the first cell row. The second fin shaped structure extends across the first cell row, and separated from the first fin shaped structure. The third fin shaped structure extends across the second cell row. The fourth fin shaped structure extends across the second cell row, and separated from the third fin shaped structure. The first to fourth fin shaped structures are arranged in order along the first direction, each of the first, second and fourth fin shaped structure has a first conductive type, the third fin shaped structure has a second conductive type.